Earnings Call Transcript - QUIK Q1 2025

Operator, Operator

Ladies and gentlemen, good afternoon. At this time, I'd like to welcome everyone to QuickLogic Corporation's Fiscal First Quarter 2025 Earnings Conference Call. As a reminder, today's call is being recorded for replay purposes through May 20th, 2025. I'd like to turn the conference over to Ms. Alison Ziegler of Darrow Associates. Thank you. You may begin.

Alison Ziegler, IR, Darrow Associates

Thank you, operator, and thanks to all of you for joining us. Our speakers today are Brian Faith, President and Chief Executive Officer; and Elias Nader, Senior Vice President and Chief Financial Officer. As a reminder, some of the comments QuickLogic makes today are forward-looking statements that involve risks and uncertainties, including but not limited to statements regarding our future profitability and cash flows, expectations regarding our future business, and statements regarding the timing, milestones, and payments related to our government contracts, and statements regarding our ability to successfully exit SensiML. Actual results may differ due to a variety of factors, including delays in market acceptance of the company's new products, the ability to convert design opportunities into customer revenue, our ability to replace revenue from end-of-life products, the level and timing of customer design activity, market acceptance of our customers' products, the risk that new orders may not result in future revenue, and other business interruptions that could disrupt supply or delivery of or demand for the company's products. For more detailed discussions of the risks, uncertainties, and assumptions that could result in those differences, please refer to the risk factors discussed in QuickLogic's most recent filed periodic reports with the SEC. QuickLogic assumes no obligation to update any forward-looking statements or information. In today's call, we will be reporting non-GAAP financial measures. You may refer to the earnings release we issued today for a detailed reconciliation of our GAAP to non-GAAP results and other financial statements. We have also posted an updated financial table on our IR web page that provides current and historical non-GAAP data. Please note, QuickLogic uses its website, the company blog, corporate Twitter account, Facebook page, and LinkedIn page as channels of distribution of information about its business. Such information may be deemed material information, and QuickLogic may use these channels to comply with its disclosure obligations under regulation updates. A copy of the prepared remarks made on today's call will be posted on QuickLogic's IR web page shortly after the conclusion of today's earnings call. I would now like to turn the call over to Brian. Go ahead, Brian.

Brian Faith, President & CEO

Thank you, Alison. Good afternoon, everyone, and thank you all for joining our first quarter 2025 conference call. Last quarter, I stated that we expected to be awarded the first of two eFPGA Hard IP contracts for Intel 18A designs within weeks, and the second one very shortly after that. I forecasted the combined value would be mid-seven figures, and if awarded in the expected timeframe, that the revenue would be recognized in Q2. The first of these contracts was awarded a few weeks ago after our last conference call, and on April 28th, we announced that we delivered design-specific eFPGA Hard IP for the customer's Intel 18A test chip. The second contract is with the same customer, but for a different program. The customer has advised us that it has been awarded funding for the program, but funding for the production ASIC, which is a subcomponent of the program, will not be awarded until Q4. Due to this delay, our revenue guidance for Q2 is $4 million. While disappointing, it does not change our full-year outlook for solid revenue growth, non-GAAP profitability, and positive cash flow. Let's take a moment to discuss the test chip program. Given the fact Intel 18A is a new process and incorporates some state-of-the-art features, such as power via backside power delivery network that we are using in our eFPGA Hard IP, we determined having a test chip would be a good investment. To do a test chip on our own would have cost millions of dollars, so we contributed our eFPGA Hard IP license in kind for access to the customer's test chips. These test chips will enable us to fully characterize the power consumption and performance, which will enable prospective customers to lower their risk assessment of our eFPGA Hard IP on Intel 18A Silicon. Our rapid delivery of the design-specific eFPGA Hard IP for the test chip has also brought us closer to this key customer. As a matter of fact, during a high-level meeting with the customer in early May, a third design for a chiplet fabricated using Intel 18A was outlined that we hope to secure later this year. We have invested heavily to gain our unique position as the first available source for eFPGA Hard IP for Intel 18A, and Intel Foundry has acknowledged our work and progress. Last summer, we announced that we joined the Intel Foundry Accelerator IP and USMAG alliances, and we have recently been named a partner in the Intel Foundry Accelerator Chiplet Alliance. As some of you are aware, I was invited by Intel Foundry to present from the main stage at Intel Foundry Direct Connect 2025. This was quite a unique honor in that QuickLogic was one of only four companies to present in the ecosystem spotlight to an audience of more than 1,000 people. The other three were Cadence, eMemory, and Synopsys. Intel Foundry confirmed that Intel 18A is in risk production with Panther Lake scheduled for mass production by year's end. Our value proposition is integration, which is what has driven this growth of the semiconductor industry since the invention of the integrated circuit 65 years ago. By using our unique eFPGA Hard IP design engineers can integrate the benefits of a discrete FPGA by embedding it in their ASIC and SoC designs or with a chiplet solution. As it stands today, we are the only company offering eFPGA Hard IP for Intel 18A technology that enables this integration. Pairing a discrete FPGA with an ASIC or SoC is very common in USMAG designs, where the total market for discrete FPGA devices is approximately $1.5 billion. The defense industrial base is very interested in using Intel 18A for new designs, and their frequent use of FPGA technology bodes very well for our unique position. While capitalizing on this interest is a strong focus, we are also rapidly building momentum in various commercial markets, including several new Intel 18A opportunities. On April 24th, we announced the inclusion of our eFPGA Hard IP in the new Faraday FlashKit 22RRAM SoC development platform. This is the UMC 22 nanometer design win we announced in November 2023. Faraday is a Taiwan-based semiconductor company with a market capitalization of approximately $1.5 billion. Its core business model is to help its customers develop ASIC and SoC designs and then storefront those designs. The primary purpose of an ASIC or SoC is to integrate as many discrete chip functions as possible into a single device, and our IP enables that integration to include discrete FPGA devices. We believe this platform will generate production eFPGA Hard IP license revenue beginning in the second half of 2025 and royalty revenue in future years. We believe there will be opportunities to expand our involvement with Faraday going forward. Notably, Faraday was one of three companies that was prominently displayed at Intel Direct Connect as a value chain alliance partner. There are four important takeaways from these data. One, Faraday's focus on commercial applications will help accelerate our expansion into new end markets. Two, Faraday's success underscores the industry demand for and value of a storefront business model. Three, our IP enables the integration of discrete FPGAs that are often paired with ASIC and SoC devices. We believe this is a meaningful subset of the $12 billion discrete FPGA market. And four, the Faraday development platform is likely to win many unique customer designs that will generate IP license and royalty revenue for QuickLogic that will scale very favorably. We announced the fourth award of the Strategic Radiation Hardened FPGA government contract valued at approximately $6.6 million last December. Following that, about six weeks ago, we announced an additional $1.4 million incremental funding modification which extends the fourth tranche. We have requested permission to share some details about the expanded scope of this contract with our investors, but so far that permission has not been granted. That said, I can tell you the device we are developing addresses a number of strategic and space applications where total dose and single event radiation hardness is critical, and the designs must include the flexibility only FPGA technology can provide. As a matter of fact, several customers have already expressed interest in using the resulting design via QuickLogic's storefront once it is completed. Now let me take a moment to update our progress on existing contracts that are scheduled to contribute to our eFPGA Hard IP revenue in 2025 and beyond. A number of these contracts have achieved significant milestones during the last several months. These include tape-out and, in several cases, test chips that have been completed and are in validation. This is important because, in some cases, test chip validation will lead to an IP production license and, in a few cases, new eFPGA Hard IP contracts. These are also good illustrations that a long tail of revenue is commonly attached to our eFPGA Hard IP contracts, and following that, a stream of royalties or storefront revenue that can extend for years and, in some cases, more than a decade. Let's start with the IP contracts. Our first contract targeting the Global Foundries’ or GF's 12-LP fabrication node is with a defense industrial-based customer and includes two cores. We completed our initial deliverables for the first core during Q3 and the second core during Q4 of 2024. In accordance with the forecast I shared last quarter, we had nominal revenue recognition in Q1 and anticipate similar revenue recognition in Q2 in support of the customer's test chip development. Last quarter, we announced an eFPGA Hard IP contract with a new defense industrial-based customer valued at $1.1 million that will also be fabricated on the GF 12LP node. Due to the fact we already had eFPGA Hard IP established for that node, we will recognize revenue and record cash flow in Q2 and Q3 2025. Our first contract for TSMC's 12-nanometer fabrication node is with a large, well-known international company. This design is for a new ultra-low-power SoC targeting a variety of commercial and industrial IoT AI applications. The customer is currently evaluating test chips, and we expect a decision about a second SoC design during Q2. In September 2023, we announced the leading technology company that shows our eFPGA Hard IP for a design that will be fabricated using GF's 22FDX platform. Test chips have been received and are in evaluation. If all goes as planned, we anticipate revenue recognition of a production license during the second half of 2025. The following are IP services contracts that we believe will be supplied via our storefront program. In November 2022, I shared that we taped out a new device for a customer that incorporates our eFPGA Hard IP. While we remain in a holding pattern due to a delay with one of the customer subcontractors, we continue to believe we will resume work during the second half of 2025 and that this design has very substantial storefront potential starting in a couple of years.

Elias Nader, SVP & CFO

Thank you, Brian, and good afternoon, everyone. Total first quarter revenue was $4.3 million, and approximately $300,000 above the midpoint of our guidance range. This upside was driven by a customer that pulled in new product shipments to Q1 that were previously scheduled for Q2. Total revenue was down 28% from Q1 2024 and down 24% compared to Q4 2024. New product revenue in Q1 was $3.8 million, down 23% from Q1 2024 and down 19% compared to Q4 2024. The decreases in total revenue and new product revenue from prior periods were mostly due to the timing of certain large eFPGA IP contracts. Non-GAAP gross margin in Q1 was 45.7%. This was below the midpoint of our outlook due to the fact approximately $300,000 of R&D costs that we projected would be allocated to OpEx were allocated to COGS. This compared with a non-GAAP gross margin of 71.3% in Q1 2024, and 62.9% in Q4. Non-GAAP operating expenses in Q1 were approximately $3 million. This was approximately $200,000 below the midpoint of our outlook, and due to the COGS allocation I just mentioned above. This compares with non-GAAP operating expenses of $2.5 million in the first quarter of 2024, and $2.9 million in the fourth quarter of 2024. Non-GAAP net loss was $1.1 million, or $0.07 per diluted share. This compares to non-GAAP net income of $1.7 million, or $0.12 per diluted share, in Q1 2024, and a non-GAAP net income of $0.6 million, or $0.04 per share, in the fourth quarter of fiscal 2024. The difference between our GAAP and non-GAAP results is related to non-cash, stock-based compensation expenses, and restructuring costs. At the close of Q1, total cash was $17.6 million, inclusive of a $15 million credit facility. This compares with $21.9 million inclusive of an $18 million credit facility at the close of Q4 2024. The primary driver for cash use during Q1 was the timing of payments to our subcontractors for the Strategic Rad Hard FPGA contract. Additionally, changes in accounts receivable, contract assets, and accounts payable resulted in a little more than $1.1 million in cash usage. We completed the integration of Simplify into AuroraPro, and setting aside some modest costs for further refinements, completed our development of Intel 18A Hard IP during Q1. While these were significant investments, we believe they will produce very impressive ROI going forward. As Brian noted, we are currently the only source for eFPGA Hard IP for Intel 18A, and have delivered design-specific IP for customers' test chip. With this unique position, we anticipate winning production contracts in 2025 and beyond. Now moving to our guidance and outlook for the second quarter of fiscal 2025, which will end on June 30th. Revenue guidance for Q2 2025 is approximately $4 million, plus or minus 10%. Second quarter revenue is expected to be comprised of approximately $3.4 million in new products, and $0.6 million in mature products. As Brian stated in his remarks, the lower-than-anticipated Q2 revenue guidance is attributable to the delay of a large IP contract that we currently anticipate will be awarded in Q4 2025. Based on the anticipated Q2 revenue mix, non-GAAP gross margin for the second quarter is expected to be approximately 50% plus or minus 5 percentage points. The lower gross margin is attributable to the unfavorable absorption of fixed costs due to lower revenue. With a significant revenue rebound, we anticipate beginning in Q3, we are modeling a full-year non-GAAP gross profit margin will be in the low 60% range. Our Q2 non-GAAP operating expenses are expected to be approximately $3 million, plus or minus 5%. After interest and other income, we currently forecast that our Q2 non-GAAP net loss will be approximately $1.1 million to $1.2 million, or $0.07 to $0.08 per share. As a reminder, there will be movements in our stock-based compensation during the year, and it may vary each quarter based on the timing of grants. We are anticipating Q2 cash flow from operations to be relatively flat, and our scheduled payments to subcontracts for our SRH contract are approximately 50% lower than they were during Q1. While having the aforementioned ATM in place provides us with flexibility, we are not currently planning to access it during Q2. As Brian noted earlier, for the full year 2025, we are anticipating solid revenue growth, non-GAAP profitability, and positive cash flow. Thank you. With that, let me now turn the call back over to Brian for his closing remarks.

Brian Faith, President & CEO

Thank you, Elias. As I mentioned earlier, I was selected by Intel to present the QuickLogic story from the main stage at Direct Connect 2025. My presentation was very well received, and based on the feedback we received, gave our core value proposition a huge shot of credibility. If you boil down our value proposition to just one thing, that thing would be enabling integration, and that is what has driven the semiconductor industry since the IC was invented 65 years ago. Our primary target markets are designs that typically have a discrete FPGA sitting next to an ASIC or SoC. That is a very common practice in USMAG designs, where discrete FPGA revenue was approximately $1.5 billion in 2024. This market opportunity, the very high qualification cost DIBs have for every discrete device, and their intense focus on size, weight, area, power, and cost, are the reasons we prioritized USMAG as we built our foundation for eFPGA Hard IP. If you review the Faraday website, you'll see this pairing of a discrete FPGA with an ASIC or SoC is also more common than you might think in commercial designs. We believe the Faraday FlashKit development platform that integrates our eFPGA Hard IP in its SoC will lead to a number of contracts in commercial markets. Also intriguing to note about Faraday's success is its very tight focus on storefront. Faraday manages storefront services for the vast majority of its contracts, and with that, reported nearly $0.5 billion in revenue over the trailing 12 months. To be clear, our sales through Faraday to its customers will be eFPGA Hard IP contracts. However, we believe a growing number of our direct IP customers will have interest in QuickLogic handling storefront services. As a matter of fact, we booked our first direct-to-storefront contract earlier this year, and we have several contracts we believe will end up being storefront. We see this as a trend for QuickLogic. As we have tried to outline for you in this call, 2025 has started out more slowly than we anticipated. However, beneath the numbers, momentum is building rapidly, and we are confident that we will post solid revenue growth, non-GAAP profitability, and positive cash flow for a full year 2025. Not only that, we also believe we will build momentum throughout the year to set us up for solid growth for years to come. Thank you. I'd now like to open the call for questions.

Operator, Operator

Thank you. We will now be conducting a question-and-answer session. The first questioner is from Quinn Bolton from Needham & Company. Please go ahead.

Quinn Bolton, Analyst

Thanks for taking my question. Brian, maybe just talk us through the ramp of Intel 18A. You guys have done a couple of test chips. Now as that starts to move to production, is your revenue stream mostly just royalties on the customer solution and being also just aggressive? Is this customer starting in commercial markets? Or is it more of a defense or risk-based application? And then I've got a follow-up. Thanks.

Brian Faith, President & CEO

Hey, Quinn, the audio is a little garbled, but I think if I repeat the question, you're asking about sort of the progress of Intel 18A in general and our timing of different IP that we've done for that leading up into revenue and royalties in the future. Is that right?

Quinn Bolton, Analyst

Yeah, that's right. Sorry for the background noise.

Brian Faith, President & CEO

Okay. Yeah, so I guess if we rewind a year when we first got access to the PDK Version 1.0, this was definitely the first time that we designed something on this modern of a process technology, this sort of state-of-the-art. Definitely took a lot from our team to get that going, a lot of EDA tools, a lot of focus on that. But once we had it ported to that technology, we started to appreciate some of the capabilities of it, like the power via backside power that I mentioned earlier. We realized that we got a really good IP core out of this in terms of power and die size because of those capabilities that we took advantage of. I think that as we started engaging more primarily with the defense industrial base, they're looking for things that are further down the TRL curve than just paper tigers or PowerPoint. When I say TRL curve, I'm talking about technology readiness level. It's from one to nine. One is through your paper simulations and nine is your in-flight on things. By us participating in this test chip that we've talked about, this actually helps accelerate further down the TRL curve in the eyes of prospective customers, especially defense industrial base ones. That was sort of the tipping point where we were able to carry these additional customer conversations forward into more timing-related discussions, commercial-related discussions, and understanding when they're planning to tape out their own test chips. So I think that's all to say that we do have 18A license revenue forecasted this fiscal year, not just that one that we mentioned that's shifted to Q4, but even before that from some other customers, including commercial ones. I think the fact that Intel last week at the conference said they're in risk production, even on their own Panther Lake processor kind of shows that it's good enough for production in many cases.

Quinn Bolton, Analyst

The value of the test chip, my guess is it's a certain size fabric that you're testing out on the test chip. The fact that you're just testing out a given size fabric is enough to convince other customers that says, hey, this is real, it's working. And if we change the size or the configuration, it's still enough in terms of their eyes to sort of give them confidence to move forward on new designs.

Brian Faith, President & CEO

It absolutely is because once you prove out a common denominator for the logic and the routing and the memory and the DSP blocks, most customers believe that if you can do that for that size, that if you need to stamp and repeat a bigger array size for them, that we can do that. And they know that that's sort of our model with Astralis. We're sort of making almost like a memory compiler out of it for FPGA technology. Once we prove out the first one for power and timing, that's all stamp and repeat for bigger array sizes. The beauty of our models is we can do that in a matter of weeks, which is well within the cycle of what they need to do for an 18A type ASIC.

Quinn Bolton, Analyst

Got it. And then the second question I had, just so you guys are looking for profitability for the full year, obviously a strong revenue ramp. Just wondering if you could kind of, what are the two or three maybe biggest drivers of that revenue ramp through the year. Obviously you've talked about Intel 18A revenue. You've talked about the Rad-Hard contract. What are the key programs that drive that nice revenue growth into the second half? Thank you.

Brian Faith, President & CEO

Yeah, I can take that. So our base business that's here every quarter is our ongoing Antifreeze FPGA business, what we call mature products, and then the strategic Rad-Hard contract. With that contract that we signed for the Rad-Hard contract last December, and then the incremental funding modification that was added on top of that in the last few months, we have good visibility of that program for the rest of this year. The new revenue driving the strong second half growth, we are forecasting income from these IP contracts, some of which are just IP and some of which are storefront. If you drill into the numbers, we have come out with two 12 nanometer process ports, and now we've got this one for Intel 18A. All of those have substantially higher average selling prices than the stuff that we were doing years ago on 22 and more mature nodes. You don't have to close a lot of designs to get strong revenue growth, and like I was just answering on your first question, we are seeing a lot of strong interest on Intel 18A now.

Quinn Bolton, Analyst

Thank you, Brian. Thank you, Elias.

Operator, Operator

Next question is from Rick Neaton from Rivershore Investment Research. Please go ahead.

Rick Neaton, Analyst

Hi, Brian. Hi, Elias. Thanks for taking my questions tonight. My first question is you mentioned in your closing remarks, Brian, about several storefront opportunities. We know about one, which is the direct-to-storefront you announced, and you've also mentioned that the Strategic Rad-Hard contract could lead to storefront. Can you provide any color on what other opportunities you have for storefronts percolating in your funnel or in the itemized list of projects you've already provided?

Brian Faith, President & CEO

Sure. Just to add one more to that list, we have the November 2022 tape-out customer. Between that and this more recent one that we just announced on the last call, the direct-to-storefront, and, of course, the biggest of which is the Strategic Rad-Hard opportunity, those are contracted ones. If we move to things in the funnel, we have a handful of ones that we've either proposed through the government RFP process, where people are looking at seeding different technologies to help build a chiplet ecosystem. We have that.

Rick Neaton, Analyst

Okay, thanks for that explanation. That's helpful. You talked about the $1.5 billion FPGA market in USMAG, and your unique value proposition is enabling integration. Is the catalyst that you think you will be, that will enable you to make a dent into that addressable market, the ability to lower the cost of verification of a product?

Brian Faith, President & CEO

Yes. If you step back for a moment, that $1.5 billion obviously is a big number. Almost 75% of DoD systems use FPGAs today, so it's not a lot of money in a few systems. It's a lot of money in a lot of systems. Almost all of these systems are also doing ASICs, custom ASICs, or SoCs by the Defense Industrial Base. Why are they doing ASICs? A lot of times they're doing ASICs because they can't quite get functionality out of standard products. It could be that they need to have something that's of the critical nature that's designed and manufactured onshore. It could just be that they need to obfuscate their IP. It could also be that they're looking to lower SWAP. These are all legitimate reasons why the Defense Industrial Base is looking at doing ASICs. And again, why would you do a $150 million ASIC and then go buy a lot of FPGAs and stick it right next to that same ASIC? If you have the opportunity to integrate that into the same chip, not only are you going to get lower SWAP-C by having it all integrated together, yes, to your point, you can also reduce your qualification costs and your verification costs. A lot of the cost of verifying is the people time. If you can just do that on one chip, you're saving a lot of time. But in order to get to that step of integration, you have to feel comfortable that the technology itself is far enough along that TRL curve I mentioned earlier, and that's why test chips are incredibly important and impactful for the Defense Industrial Base.

Rick Neaton, Analyst

Okay. One final question. Faraday was originally part of UMC, or came from UMC?

Brian Faith, President & CEO

It was a spin-off, yes.

Rick Neaton, Analyst

Are your opportunities with Faraday limited to the node that the part that was announced works on, or are you looking at maybe going smaller, like at the 12-nanometer node that UMC is working with Intel on?

Brian Faith, President & CEO

I would love to go smaller. Obviously, we have a big focus on selling what's available today, and so there's a big focus on doing what we can do and helping them with the 22 nanometer. It's probably like they're doing something on 12 with UMC. The more comfortable they get with the notion of embedded FPGA in a SoC, the more amenable it is to jump to that next node. And the next node is probably not just for cost reasons; it's going to be for use case and applications and end markets. We want to see that it's portable to the next thing, and 12 is clearly one of those.

Rick Neaton, Analyst

Thanks, Brian. Thanks, Elias.

Operator, Operator

Next question is from Richard Shannon from Craig Hallam. Please go ahead.

Richard Shannon, Analyst

Thanks, Brian and Elias, for taking my questions. Brian, I guess the first question is, this $1.5 billion of FPGA revenues for USMAG, I think the way that you referred to it made it sound like it was just for Intel 18A-related stuff here, but it seems like the Strategic Rad-Hard would also kind of cover the same thing. So I just want to clarify, what is that exactly covering?

Brian Faith, President & CEO

That's an estimate of total FPGA usage by the USMAG on an annual basis, not specific to 18A. Apologies if I gave that impression. That's the annual programmable logic market today in revenue. Now, the Strategic Rad-Hard one would obviously fall under discrete FPGA. To get some of the capability that we're designing into that, you would actually have to go to your own ASIC.

Richard Shannon, Analyst

Okay. That makes sense. That's helpful. Okay. Now I understand that a little better. Thanks for clarifying that one. Let's step over to the Rad-Hard program here. I guess my core question here is trying to get a sense of when you think we're going to start to see storefront revenues pop up here.

Brian Faith, President & CEO

We're waiting into areas that I have asked for permission to share, and I've been denied that request. I can't give hard years as dates as much as I would like to, but let me try to give some contextual information. We've been doing this development since August of 2022. When we signed that first contract, it was outlined as a four-year development. I've talked about, I think a lot more engagement with the defense industrial base, which means getting closer to getting them something they can start evaluating.

Richard Shannon, Analyst

Okay. I'll look forward to the time when you actually get permission to talk about that. That'll be a very interesting conversation. Maybe touching quickly on Faraday, probably more of a clarification.

Brian Faith, President & CEO

Faraday will be licensed and royalty because they're the ones ultimately selling a storefront device to customers. Our point in bringing them up is a good exemplar for the storefront model where you start as services and IP but ultimately are providing the supply chain services to the customer.

Richard Shannon, Analyst

All right. Maybe my last question here, and I made this from either of you. I think you've talked about from a yearly perspective here, getting to profits and gross margins, I think it's 60% or something like that, but you talked about solid revenue growth. Anyway, you'd want to give us a sense of what that means quantifying.

Elias Nader, SVP & CFO

Well, it's not 30%. It's Elias, by the way, Richard. It's not 30% for sure, but since we don't give a yearly outlook, we expect a decent rebound in the second half. Let's put it this way. That gives us confidence to be profitable and to end the year with cash flow positive.

Richard Shannon, Analyst

I think that is going to be all for you guys. Thanks for taking my questions.

Operator, Operator

Thanks, Richard. Our next question is from Martin Yang from Oppenheimer. Please go ahead.

Martin Yang, Analyst

Hi, thank you for taking the question. My first question is a follow-up on Faraday. So in this partnership, do you expect Faraday to take on the majority of the go-to market to sell the chip? Are you taking on any sales responsibilities?

Brian Faith, President & CEO

They will be the primary interface to their customer. We are enabling their sales force with different use cases and documentation and training. Faraday will be the point person for those customer engagements directly.

Martin Yang, Analyst

Got it. And can you give us a sense of the most applicable end markets or devices that those chips will go into?

Brian Faith, President & CEO

Their focus is around low power, industrial and IoT applications. The level of processing is definitely more than just the basic microcontroller. You could run some pretty good applications, including running a full operating system with a user interface and GUI. I think it would be applicable for low power edge applications.

Martin Yang, Analyst

Thanks, Brian. That's it for me.

Brian Faith, President & CEO

Okay. Thanks, Martin.

Operator, Operator

This concludes the question-and-answer session. I'd like to turn it back to Brian Faith for any closing comments.

Brian Faith, President & CEO

Thank you for joining today's call. Before we conclude, I'd like to highlight a few upcoming events where QuickLogic will be participating. May 21st, the Ladenburg Technology Innovation Expo in New York. If you are interested in meeting with us there, please contact Alison for details on how to register. June 23rd, we'll be at the Chips and Systems Conference, formerly known as DAC, in San Francisco. And on July 14th, we will be in Tennessee at NESREC. We hope to see you at these events. As always, we appreciate your time, interest, and continued support. And we look forward to sharing our continued progress with you in August. Thank you and goodbye.

Operator, Operator

This concludes today's teleconference. You may disconnect your lines at this time. Thank you again for your participation.