Greetings. Welcome to the Aehr Test Systems Fiscal 2026 Second Quarter Financial Results Conference Call. Please note, this conference is being recorded. I will now turn the conference over to your host, Jim Byers of PondelWilkinson, Investor Relations. You may begin.

Thank you, operator. Good afternoon, and welcome to Aehr Test Systems Second Quarter Fiscal 2026 Financial Results Conference Call. With me on today's call are Aehr Test Systems' President and Chief Executive Officer, Gayn Erickson; and Chief Financial Officer, Chris Siu. Before I turn the call over to Gayn and Chris, I'd like to cover a few quick items. This afternoon, right after the market closed, Aehr Test issued a press release announcing its second quarter fiscal 2026 results. The release is available on the company's website at aehr.com. This call is being broadcast live over the Internet for all interested parties, and the webcast will be archived on the Investor Relations page of the company's website. I'd like to remind everyone that on today's call, management will be making forward-looking statements that are based on current information and estimates and are subject to a number of risks and uncertainties that could cause actual results to differ materially from those in the forward-looking statements. These factors are discussed in the company's most recent periodic and current reports filed with the SEC. These forward-looking statements, including guidance provided during today's call, are only valid as of this date, and Aehr Test Systems undertakes no obligation to update the forward-looking statements. Now with that, I'd like to turn the conference call over to Gayn Erickson, President and CEO.

Thanks, Jim. Good afternoon, everyone, and welcome to our second quarter fiscal 2026 earnings conference call. I'll begin with an update on the key markets we're targeting for semiconductor test and burn-in, with a particular focus on the common growth drivers we're seeing across these markets, which is namely the massive explosion of AI and data center infrastructure. After that, Chris will walk through our financial performance for the quarter, and then we'll open up the call for questions. While second quarter revenue was softer than anticipated, we made significant progress in both wafer-level burn-in and packaged-part burn-in segments and are very excited about our prospects moving forward. Based on customer forecasts recently provided to Aehr, we believe our bookings in the second half of this fiscal year will be between $60 million and $80 million, which would set the stage for a very strong fiscal 2027 that begins on May 30. During the quarter, we made substantial progress with wafer-level burn-in engagements and production installations across AI processors, flash memory, silicon photonics, gallium nitride, and hard disk drives. We're encouraged to see that one of our key growth strategies focused on reliability solutions for the exploding demand for AI and data center infrastructure is beginning to bear fruit. In packaged-part burn-in, we secured key new device wins for our Sonoma system supporting high-temperature operating life qualifications for AI devices. These wins are expected to drive additional capacity at test houses, including at least one customer that has elected to move into production in late calendar 2026, which we believe could result in meaningful volumes of Sonoma production systems. In addition, in the last month, we received a very large forecast from our lead Sonoma production customer for AI ASIC production capacity. This forecast is expected to drive very strong and potentially record bookings for the company this fiscal year and position us well for significant revenue growth next fiscal year with their requested shipments starting in the first fiscal quarter of our next fiscal year. Taken together, our increased visibility across multiple end markets gives us great confidence in our outlook. As a result, we're reinstating financial guidance in fiscal 2026, which we'll touch on later in today's call. Now let's talk about our key segments. Starting with our wafer-level burn-in during the quarter, we expanded engagements and completed additional production installations across several end markets. Our lead AI wafer-level burn-in customer continues development of its next-generation processor and is currently discussing additional capacity with us. They're forecasting additional system and WaferPak capacity orders this fiscal year and plan to transition to our fully integrated automated WaferPak aligner for 300-millimeter wafers. We expect this customer to continue scaling and are excited to support their growth. We also announced a strategic expansion of our partnership with ISE Labs during the quarter to deliver advanced wafer-level test and burn-in services for next-generation high-performance computing and AI applications. This partnership accelerates time to market, improves performance, and gives customers the option of either packaged-part or wafer-level test and burn-in for their production volumes. ISE, together with its parent company, ASE, represents the world's leading outsourced semiconductor assembly and test, or OSAT platform, serving a global roster of top-tier semiconductor customers. As part of our benchmark evaluation program with a top-tier AI processor supplier we announced last quarter, we completed development of our new fine-pitch WaferPaks for wafer-level burn-in of high-current AI processors. These are currently in test with this potential customer's processors and are designed to validate our FOX-XP production systems for wafer-level burn-in and functional test of their high-performance, high-power AI processors. We're currently completing start-up procedures such as power-up sequencing, thermal profiling, test vectors, timing, and high-speed differential clocks and expect to complete data collection this quarter. While we're demonstrating our new fine-pitch high-current WaferPaks for this benchmark, many customers can utilize lower-cost WaferPak designs if certain design-for-test rules are incorporated upfront. These approaches reduce cost and lead time and are especially attractive to customers focused on faster time to market for wafer-level high-temp operating life qualification. We also have two additional AI processor companies planning wafer-level benchmark evaluations since last quarter's earnings call. These benchmarks typically take about six months, and we expect to make meaningful progress beginning this quarter. Both customers are evaluating wafer-level test and burn-in as an alternative to packaged-part or system-level test for large advanced AI modules that combine multiple AI accelerators and stacked high-bandwidth memory. Moving burn-in upstream to the wafer level significantly reduces cost and yield risk by avoiding scrapping expensive substrates and memory stacks when early failures occur later in the process. We have seen estimates that show the cost of the substrate is more than a single processor, and the cost of the high-bandwidth memory is even higher. Turning to flash memory. We completed our wafer-level benchmark with a global leader in NAND flash just prior to the holidays. The customer has now taken the wafers back for further processing to validate correlation with their internal process. This benchmark demonstrated our ability to test flash memory wafers with significantly higher parallelism and power than is possible using traditional probers and group probers from companies such as TEL or ACCRETECH. We've also proposed a next-generation solution enabling test of a new emerging flash memory device called High Bandwidth Flash or HBF, designed for AI workloads. This proposed solution leverages our FOX-XP platform, WaferPaks, and auto-aligner technology, and would support single touchdown high-power test on 300-millimeter wafers. While development of this system would take over a year following customer commitment, we believe this represents a compelling entry point into a large and evolving memory market. We look forward to sharing more details as this progresses. Turning to silicon photonics. We believe that silicon photonics used in data centers and also chip-to-chip I/O is going to be a significant market driving production burn-in capacity for our FOX wafer-level burn-in systems and WaferPaks. Our lead customer has now firmed up its production ramp, which we expect to begin early next fiscal year. While this timing is later than previously expected, it aligns with recently announced AI processor platforms and positions us well for calendar 2026 orders and deliveries in fiscal 2027. We've also finalized a forecast with another major silicon photonics customer initially targeting data center applications with a roadmap toward optical I/O. We expect to book their initial turnkey FOX system soon with delivery planned for May of this year. In gallium nitride power semiconductors, we continue to support our lead production customer, though we experienced delays related to unanticipated high-voltage fault conditions that required WaferPaks and protection circuit redesigns. This delayed approximately $2 million in WaferPak shipments from last quarter into this quarter, along with some in-system enhancements. Shipments have now resumed, and lessons learned have significantly strengthened our GaN power supply burn-in capability. If anyone tells you that testing and burning-in full wafers of GaN power semiconductors with up to 600 volts or more is easy, don't listen to them. We also continue to engage with multiple new potential GaN customers and are developing WaferPaks for several new device designs that are expected to go to high-volume production for applications like data center infrastructure and power delivery, automotive electrical power distribution on both ICE and hybrid electric vehicles, and even power semiconductors used for electrical breakers. Aehr has a unique solution that can deliver full turnkey, fully automated wafer handling and probing for test and burn-in of GaN wafers in sizes from 6 to 8 inches and even 12 inches or 300-millimeter wafers. Turning to silicon carbide. As we previously discussed, silicon carbide demand has been weighed toward the end of this fiscal year. Customers continue to be optimistic about this market and their capacity needs. But we've tried to take a very conservative stance that is mostly show us the orders before we believe them. Our lead customer recently transitioned from 150 millimeters to 200-millimeter wafers, nearly doubling output without adding new FOX-XP systems and supported by Aehr's proprietary WaferPaks that we developed to accommodate both 150 and 200-millimeter wafers contacting 100% of the die on each in a single touchdown. They're now seeing additional needs for WaferPaks this year, but additional capacity for systems appears to be a year out. We pushed out expected orders until next fiscal year from our near-term forecast, but have capacity of systems or WaferPaks to continue to support their surge capacity needs as well as our other silicon carbide customers. While electric vehicle-related demand has slowed industry-wide, we remain well positioned with the most competitive wafer-level burn-in solution available, and we expect to benefit when growth resumes. In semiconductors used in data center hard disk drives, we're installing the additional FOX-CP systems for a major supplier of hard disk drives for wafer-level burn-in of their special components in their drives. They've indicated plans for additional purchases later this calendar year. While their device unit volumes are very large, the overall revenue opportunity remains modest due to short stress times and the massive parallelism achieved on our FOX-CP system and proprietary high-power WaferPak wafer contactors. Now let me talk about packaged-part burn-in. We're seeing continued momentum in packaged-part qualification and production burn-in for AI processors, driving growth in our new Sonoma ultra-high-power packaged-part burn-in systems and consumables. As we announced today in a separate press release, during our fiscal third quarter to date, we have received orders from multiple customers totaling more than $5.5 million for our Sonoma ultra-high-power packaged-part burn-in systems, including initial orders from a premier Silicon Valley test lab for our newly introduced higher-power configured Sonoma system that can also support full automation. These orders already exceed the total Sonoma orders for the entire second quarter, highlighting the accelerating demand we're seeing for our package-level burn-in of high-powered AI and compute devices. This quarter, we also secured key new device wins on the Sonoma platform for high-temp operating life qualification. These wins are expected to drive additional capacity at test houses, with at least one customer planning to transition to production later this calendar year, generating significant system demand. Our lead packaged-part burn-in production customer for AI processors continues to ramp and is forecasting substantial growth in 2026 and beyond. Although we have not yet received the purchase order, we have received a substantial forecast from this customer for AI ASIC production capacity with requested Sonoma production, packaged-part burn-in system, and BIM shipments beginning in the fiscal first quarter of 2027. That starts May 30, which we expect to contribute to very strong bookings in fiscal 2026 and generate significant revenue growth in fiscal 2027. This customer also plans to introduce much higher power ASICs later this year for which we are already developing the high-temp operating life qualification burn-in modules and sockets to be used on the Sonoma systems at one of the premier Silicon Valley test services companies that have many systems installed. This AI accelerator ASIC processor is also forecasted to go to production burn-in and drive even higher volume needs for production burn-in systems downstream at the OSATs in Asia. We feel we're very well positioned with our Sonoma system for this production capacity need and believe this could drive very substantial volumes of Sonoma systems in our next fiscal year. During the quarter, we completed development of a next-generation fully automated higher-power Sonoma system, supporting up to 2,000 watts per device. This system enables continuous flow operation, improved throughput, and seamless transition from qualification to high-volume production using the same fixtures and sockets. These capabilities enable customers who are focused on high-temp operating life reliability testing to have a system that is fully software and hardware compatible with the Sonoma systems they have installed, which simplifies and accelerates time to market that is critical for HTOL testing of new AI processors. This Sonoma burn-in system can also simply bolt on a fully automated handler developed and sold by Aehr Test as a turnkey solution to allow hands-free operation with less than a couple of minutes of overhead per burn-in cycle, which is amazing for production burn-in needs. We're also seeing increased demand for our lower-power Echo and Tahoe packaged-part burn-in systems, driven by our installed base of more than 100 systems across over 20 semiconductor companies worldwide. But I'll wait for another call to discuss these systems and the markets they serve in more detail. As stated last quarter, the rapid advancement of generative AI and the accelerating electrification of transportation and global infrastructure represent two of the most significant macro trends impacting the semiconductor industry today. These transformative forces are driving enormous growth in semiconductor demand while fundamentally increasing the performance, reliability, safety, and security requirements of the devices used across computing and data infrastructure, telecommunications networks, hard disk drive and solid-state storage solutions, electric vehicles, charging systems, and renewable energy generation. As these applications operate at ever higher power levels and in increasingly mission-critical environments, the need for comprehensive test and burn-in has become more essential than ever. Semiconductor manufacturers are turning to advanced wafer-level and package-level burn-in systems to screen for early life failures, validate long-term reliability, and ensure consistent performance under extreme electrical and thermal stress conditions. This growing emphasis on reliability testing reflects a fundamental shift in the industry from simply achieving functionality to guaranteeing dependable operation throughout a product's lifetime. A requirement that continues to expand alongside the scale and complexity of next-generation semiconductor devices. This year, we're making significant progress expanding into additional key markets for our semiconductor test and burn-in solutions, including AI processors, gallium nitride power semiconductors, data storage devices, silicon photonics integrated circuits, and flash memory. This diversification of our markets and customers is significant given our revenue concentration in silicon carbide for electric vehicles the last two years. This progress and key initiatives expands our total addressable market, diversifies our customer base, and provides us with new products, capabilities, and capacity, all aimed at driving revenue growth and increasing profitability. The progress we made this quarter with a significant number of customer engagements and production installations provides improved visibility into future demand. As a result, we're reinstating guidance for the second half of fiscal 2026. For the second half of fiscal 2026, which began November 29, 2025, and ends this May 29, 2026, Aehr expects revenue between $25 million and $30 million. As stated earlier, although we're not providing formal bookings guidance, based on customer forecasts recently provided to Aehr, we believe our bookings in the second half of this fiscal year will be much higher than revenue between $60 million and $80 million in bookings, which would set the stage for a very strong fiscal 2027 that begins on May 30, 2026. With that, let me turn it over to Chris, and then we'll open up the lines for questions.

Thank you, Gayn, and good afternoon, everyone. I'll begin with bookings and backlog, then walk through our second quarter financial performance, cash position, outlook, and investor activity. The company recognized bookings of $6.2 million in the second quarter of fiscal 2026 compared to $11.4 million in the first quarter. At the end of the quarter, our backlog was $11.8 million. Importantly, during the first six weeks of the third quarter, we received an additional $6.5 million in bookings. This increase was driven primarily by an order from a premier Silicon Valley test lab for our newly introduced high-power configured Sonoma system, which we announced this afternoon. Including these recent bookings, our effective backlog has now grown to $18.3 million, providing increased visibility as we move through the remainder of fiscal 2026. Turning to our second quarter results. Revenue was $9.9 million, down 27% from $13.5 million in the prior year period. The decline was primarily driven by lower shipments of WaferPaks, partially offset by stronger demand for our Sonoma systems from our hyperscaler customer. Contactor revenues, which include WaferPaks for our wafer-level burn-in business and BIMs and BIBs for our packaged-part burn-in business totaled $3.4 million, representing 35% of total revenue. This compares to $8.6 million or 64% of revenue in the second quarter last year. Non-GAAP gross margin for the second quarter was 29.8% compared to 45.3% a year ago. The year-over-year decline reflects lower overall sales volume and a less favorable product mix as last year's quarter included a higher proportion of higher-margin WaferPak revenue. Non-GAAP operating expenses in the second quarter were $5.7 million, down 4% from $5.9 million in Q2 last year. The decrease was primarily due to lower personnel-related expenses, which were partially offset by high research and development costs, including high project spending as we continue to invest resources in AI benchmark initiatives and memory-related programs. As previously announced, we successfully closed the Incal facility on May 30, 2025, and completed the consolidation of personnel and manufacturing into Aehr's Fremont facility at the end of fiscal 2025. During the quarter, we negotiated an early lease termination with the landlord, reducing our obligation by 5 months of rent. As a result, we recorded a reversal of $213,000 related to a previously accrued one-time restructuring charge. During the quarter, we recorded an income tax benefit of $1.2 million, resulting in an effective tax rate of 27.3%. Non-GAAP net loss for the quarter, which excludes the impact of stock-based compensation, acquisition-related adjustments, and restructuring charges was $1.3 million or negative $0.04 per diluted share compared to net income of $0.7 million or $0.02 per diluted share in the second quarter of fiscal 2025. Turning to cash flow. We used $1.2 million in operating cash during the second quarter. We ended the quarter with $31 million in cash, cash equivalents, and restricted cash, up from $24.7 million at the end of Q1. The increase was primarily due to proceeds from our at-the-market equity program. As a reminder, in the second quarter of fiscal 2025, we filed a new $100 million S-3 shelf registration that was approved by the SEC for 3 years, followed by an ATM offering of up to $40 million. During the second quarter of fiscal 2026, we raised $10 million in gross proceeds through the sale of about 384,000 shares. At quarter end, $30 million remained available under the ATM. We intend to utilize the ATM selectively with a disciplined approach focused on market conditions and shareholder value. Looking ahead to the second half of fiscal 2026, which began on November 29, 2025, and ends on May 29, 2026, we expect total revenue between $25 million to $30 million and non-GAAP net loss per diluted share between negative $0.09 and negative $0.05 for the 6-month period. On the Investor Relations front, last month on December 17, 2025, Lake Street Capital initiated analyst research coverage on Aehr Test, along with equity research firm, Freedom Broker, which initiated coverage last June. There are now a total of four research firms covering the company. Lastly, looking at the Investor Relations calendar, we will meet with investors at the 28th Annual Needham Growth Conference in New York on Tuesday, January 13, and then return to New York in February for the 15th Annual Susquehanna Technology Conference on Thursday, February 26. We will also be participating virtually in the Oppenheimer Emerging Growth Conference on Tuesday, February 3. We hope to see you at these conferences. That concludes our prepared remarks. We're now happy to take your questions.

Our first question comes from Christian Schwab with Craig-Hallum.

What wasn't clear to me is the potential booking strength of $60 million to $80 million in the second half of this fiscal year. Is that primarily related to the AI accelerator processor line?

There's some silicon carbide, not much, like not very much at all. There is some silicon photonics for sure. But the bulk of it is across wafer-level and packaged-part burn-in for AI processors, yes.

Okay. Perfect. And then given that such a material bookings from the AI processor market, can you give us any indication or idea? I know we've talked about the opportunity in that marketplace being bigger than silicon carbide. But let's narrow it down to kind of a multiyear time frame kind of including '27 and '28. Do you see that business after initial orders expanding meaningfully from there?

We have been taking a cautious approach regarding the potential size of the AI and wafer-level market. To be honest, we are still trying to understand the scale of it. We often receive specific insights about GPUs, CPUs, network processors, or ASICs from our customers, and we also look at external market information to correlate what we hear. Frequently, customers report higher numbers than what the market is indicating. We're unsure of the implications of this disparity. As customers provide us with estimates for test times and burn-in conditions, we start to quantify the opportunity. For major players, a single processor at wafer-level burn-in can require around 20 to 30 systems, with each costing between $4 million and $5 million. This gives us an idea of the scale involved. Currently, estimates for AI testing spend, between testing and burn-in, range from around $8 billion to $15 billion, which is a significant figure. We want to remain grounded, but when clients ask how much we can produce, it suggests that AI could eventually represent hundreds of millions of dollars for Aehr Test in the coming years. Our position is quite advantageous because our Sonoma system is a preferred choice for high-temperature operating life reliability testing of AI processors, having the largest installed base in test houses globally. We are attracting inquiries because we have more capacity than competitors, making us a go-to provider. Customers are utilizing our system, allowing us to be closely involved in their processes. We can even offer options to integrate production capabilities into our machines. During facility tours, we showcase our FOX wafer-level burn-in test cell, even though we can't disclose certain specifics. This aspect puts us in a unique position to discuss both wafer-level and packaged tests. The average selling prices are higher for wafer-level tests; however, the yield benefits of wafer-level testing far exceed the associated costs. As we gain a clearer understanding of the market, the available data will focus on packaged parts since we are the only ones currently offering wafer-level testing. We are working on our own models to assess what capacity at wafer-level burn-in would look like, similar to how we approached the silicon carbide market. We haven't yet fully assessed the size of the market, which is significant, especially considering companies like NVIDIA, Google, Microsoft, and Tesla are all utilizing our solutions.

Great. And then I guess one last question, if I may, and follow up on your comment about capacity. How many systems do you think you're capable of manufacturing in a year for wafer level?

We have talked to customers about capacities exceeding 20 systems a month at either package or wafer level. If we had to, we could ship 20 systems a month of each during this calendar year. Now that's bigger than our forecast by a lot. But you know what, when people are saying, could you do something like this and intercept something, it's like if they gave you an order for 50 or 100 Sonomas, like how long is it going to take you to build them? Makes sense?

The next question comes from Jed Dorsheimer with William Blair.

Yes, to begin with, regarding the wafer level, it appears that the timing of the benchmark is taking longer than expected. I am curious if this delay is due to the newness of the process and if the customer is making changes that are prolonging it. I recall you mentioned a timeframe around February, and we are almost...

Do you want me to criticize my customer? Is that what you're implying? I understand your point. What I aim to do is accurately convey our experiences and knowledge at the time. One interesting aspect about this notable customer is that when they provided us with the test vectors, they were coming from a package level perspective. Package and wafer are distinct, and we had extensive discussions about what could be done at the wafer level. Ultimately, we demonstrated significant DFT and lower pin count modes at the wafer level, which was crucial because they hadn't previously grasped this concept, as nobody had done that with us before. They provided some information based on package specifications that weren't fully applicable to the wafer level, and we had some difficulties because of that, which led to delays. It became clear to both parties that they had been thinking in terms of package rather than wafer, which is a learning experience. We have encountered this with other customers as well. The first time engaging in wafer level burn-in presents unique challenges, especially regarding devices sharing common substrates in a probing environment. Is it taking longer? Perhaps a few weeks or a couple of months, but mechanically, things like the wafer physical contact with our auto aligner, the new fine-pitch WaferPaks, and the test plans and vectors were advancing well. Although I wish it had progressed more quickly, I believe we are on track to provide them with data in the next couple of months, possibly even this month. The next question then becomes how they will use this information and what their timing will be. We know what device they want to implement, although we cannot disclose that information. We believe there are many reasons to proceed with wafer-level burn-in as soon as possible, and we are enthusiastic about this project. Additionally, we have other customers expressing interest in collaborating and are preparing the necessary information for design reviews and WaferPak designs.

Got it. That's helpful. I want to address the potential for cannibalization between package and wafer level. From your comments, it appears that the AI processor is progressing with this customer at the wafer level. You briefly mentioned the ASIC side. Are you expecting the ASICs to operate at package level while the AI processors are at wafer level? Or do you see both operating at wafer level?

Yes. So for everyone listening, when we discuss processors in AI, there are at least two or three main types. There are GPUs, such as those from NVIDIA or ASICs from other manufacturers. Even NVIDIA's GPUs can be considered a form of ASIC. These are AI accelerator platforms that can be used for large language models or inference tasks. Additionally, there are CPUs like those from Intel, Grace, or Vera, among others, that are also undergoing a burn-in process. You might also consider network processors. Generally, when we mention AI processors, we are referring to combinations of CPUs and GPUs or ASICs grouped together in AI processor clusters. For example, the GB200 consists of a Grace CPU and two Blackwell AI accelerators packaged together or within a single cluster. The roadmap is evolving as devices transition from having a single AI accelerator or CPU in a package to integrating embedded memory, such as high-bandwidth memory and flash, and eventually including multiple compute chips. This means that devices could have 2, 4, or even 8 processors, similar to what Intel and AMD are planning. Currently, all qualifications are being conducted on a complete package, which can take months to process. There is interest in qualifying processors while they are still in wafer form, as it allows for more efficient failure management during production. The value proposition lies in isolating failing components rather than replacing entire packages. Thus, there is growing enthusiasm for evaluating new devices, with the potential for significant performance improvements as technology evolves. There is concern about potentially missing the opportunity with certain devices, but customers are eager to explore integration options. Our key production customer, known as an ASIC hyperscaler, is currently in Sonoma production and we are working to qualify their next device for production in the same environment. They are also considering wafer-level burn-in, signaling potential shifts in how we manage package systems. Ultimately, it seems both approaches will coexist for some time, and we are well-positioned to accommodate both methods. But is there cannibalization? For sure. We had a customer come in who wanted to talk about what we thought was packaged part burn-in. Alberto, our VP over the packaged part business, and I met with them, and 15 minutes into the meeting, he goes, I'd like to talk about wafer level. Alberto looked over at me, and I'm like, okay, new slides. So at least we got both. And we're in a great position. And actually, I would say it's all three, we do the high-temp operating life today only at package over time at wafer level, and we do production burn-in either package or wafer level. So a great front row seat.

Our next question comes from Max Michaelis with Lake Street Capital.

First one for me, just around the bookings guide. I know you previously shared that the majority is around AI. But just given the distinction between the low end and the high end, if we take the midpoint of around $70 million, what would it take to reach that $80 million? Is that all basically around AI, or does that suggest any improvement in silicon carbide or GaN?

The smallest amount comes from silicon carbide, followed closely by GaN. Hard disk drive is slightly larger, while silicon photonics is a substantial portion. We have production systems in place for our lead customer and a new customer interested in a system that requires a chip by May. We’re advising them to place their order before we ship, just joking, but it is a challenge because they are eager for us to build it. We actually have a system ready, and if they send their purchase order, they can have it; otherwise, we will offer it to another client. Additionally, wafer-level burn-in follows, but the largest segment consists of wafer-level burn-in for AI and packaged parts for AI.

Okay. So the $60 million to $80 million indicates that the $80 million reflects larger volume orders for wafer level burn-in. Okay. Lastly, I haven't had time to go through the entire press release, but could you provide more details about the $5.5 million order you mentioned in your prepared remarks? Is there anything new we should be aware of, or is it just standard?

It includes various customers who already owned Sonomas and were purchasing more AI-related products. Additionally, there were some burn-in modules that were significant for a new design expected to be a high-volume production. We received a substantial order from what we refer to as our premier Silicon Valley test services company, and they purchased several of the latest high-power Sonoma configurations capable of reaching 2,000 watts. We are set to test some devices this spring that will nearly hit 2,000 watts each. While others are discussing how to achieve 1,000 watts, we are surpassing that benchmark with a high-volume Sonoma system. This will allow for testing a considerable number of devices within that system. If I recall correctly, the number is 44 devices, which is significant for testing purposes. However, it could also be 22; I need to verify that. We should consider the math regarding that specific application due to the resources and power supplies involved. Nevertheless, this is the largest development we have seen, and it is moving toward production, marking an important milestone for us. Overall, this encompasses a mix of various orders, each of which holds strategic importance to our operations.

The next question comes from Larry Chlebina with Chlebina Capital.

We aim to align your ramp or at least the demand for the systems you're developing for these customers on the AI processors with what's publicly announced regarding the product launch. Is there a possibility that they might start with a packaged part where they have the capacity for it? Then, when they're comfortable, perhaps after the product is launched, would they transition to wafer-level burn-in due to its greater efficiency and cost savings? Would they take that approach, or would they prefer to implement it solely at the start of a new product launch? Do you have any insight on that?

Okay. There are two main points to consider. Firstly, we know a customer was conducting system or rack tests. They only detected early failures when the product was installed in the data center, which is quite significant. They mentioned that if they ran it for two weeks without issues, they would accept it, and then connect it to the network, which is a costly approach. Secondly, companies like AEM, Advantest, and Teradyne have developed system-level test machines intended for fast boot-up and operating system loading. These machines offer substantial test coverage for specific applications. Some have suggested using them for burn-in, but these systems are primarily designed for speed and user mode operations, not for burn-in, and they are quite large and expensive. The market is pushing for these because they are preferable to traditional rack testing. There haven't been suitable options available for large-scale burn-in systems, often referred to as ovens, which accommodate multiple burn-in modules or trays. This is where Sonoma comes into play, as it was being utilized for Hi-Tec operating life tests. The question arose if it could also be used in production with added automation to significantly increase capacity. Thus, entering the system-level test market for rack testing doesn't seem sensible for Sonoma. Wafer-level burn-in is an even better option, though customers may need to consider where to implement it and possibly adjust their design for testing to utilize the affordable full wafer contactors from Aehr Test. Overall, it's a process of evolution. During conversations with customers, they express a need for packaging for burn-in, but they are also interested in how wafer-level burn-in could be integrated. Depending on each customer’s situation, it may not always be a matter of price but rather of yield and capacity. We have various customers with differing needs regarding wafer-level or packaged solutions, and this will evolve over time. Ultimately, we aim to meet customer needs, so we are here to listen to what they want.

Well, if you consider all these evaluations related to wafer level burn-in, if it takes longer and the product eventually gets launched, would they still transition to some portion of the production on wafer level burn-in once it’s validated for that specific product, or would they do that midstream?

I think it depends. It's not a guaranteed outcome. Traditionally, people will start a product and release it on one test platform or something similar, then they move on to the next one. That seems fair to say, but there are certain devices where we know there are two or three different intended applications. For a large language model, there might be one perspective, but automotive applications would change that. Even within a product, there could be changes, or they might operate until they can implement wafer level burn-in. This is especially relevant when considering a multichip module. As soon as wafer-level burn-in is possible, if I could save 1% yield per die on a 4-die AI processor with a $15,000 bill of materials, then it would make sense to do that.

I'm not sure if they would.

Yes. We are trying to be as transparent as possible. We understand what we can, but there are definite advantages to utilizing wafer level. In fact, that is the optimal approach. By incorporating some DFT and other techniques we employ, I can create a WaferPak for you in 8 weeks and have it ready for wafer.

I'll shift gears on the flash benchmark that you completed right a little bit ago before holidays. When do you expect the customer to get back to you and more importantly, when do you expect them to come with an order?

I was waiting for someone. Yes, I'm on the same page. I think, Larry, it will take a couple of months for them to get back, depending on how the wafer returns for testing, which occurs at the wafer level. I don’t believe they will package it and go through any stress qualification, but that could be a possibility. We have already conducted some design reviews with them regarding our new tester, and I would say they were quite impressed. The significant change occurred when we began our benchmark discussions with them about a year ago.

Yes, over 1.5 years ago.

Yes. Yes. Fair enough, right? When we were starting to even build up to get the design files and what wafer we are going to be testing with them, it was not aimed at high bandwidth flash because that didn't even exist, right? They were looking at it for like commodity data center SSDs. Now with the HBF, it broke their infrastructure, the power supplies, IO pins, et cetera, and parallelism, and now they have a power problem, which we love. Well, we're good at power. So people that have power problems that's music to our ears, so yes.

I would think they would need more capacity for the enterprise flash part of it before they ever start needing something for HBF. So the enterprise flash, I'm wondering when is something going to happen there? It seems like it's overdue.

Yes, our goal was to finish the benchmark by the end of last year, but we're about six months behind. As I mentioned, back in March, it felt like we were pushing against something that wasn’t moving. If you knew the company, it would be clear what was happening. They shifted their focus from enterprise to HBF, which slowed down the review of our tester. They returned to us in the summer with a new tester request. Although it took longer than expected, that’s part of the process. We visited them and demonstrated a fully integrated machine instead of just taking their wafer for a manual setup. We placed their wafer at the FOP, connected it to our Sierra automated WaferPak Aligner, ran the tests, and obtained impressive results.

So you're ready to go for production. So it seems like they need. They're going to need more capacity based on everything that's going on in the memory market.

Exactly. Right now, they're all benefiting from margins. So I agree, Larry, you are our biggest supporter in the memory strategy, along with me. We are indeed spending money, which is part of our approach. As Chris mentioned, we could be performing better. At our current revenue levels, we're not satisfied. We're not making money at these levels, but we would be earning more if we weren't spending. We're fully committed to growth. In fact, we expect to increase our R&D spending, especially in the AI wafer-level burn-in, with some additional investment in packaging since we've invested significantly in that area just this past year to get our new product out, along with enhancements to the memory system within our FOX system.

It should pay off. Let's hope it's soon, sooner rather than later.

I vote yes, too. As a shareholder, I think it's good money to be spent. That's all I have. Thank, Gayn. Thank you, Larry.

Okay. I'm showing no further questions in the queue. I would like to turn the call back to management for closing remarks.

Thank you, operator, and thank you, everybody. We really appreciate you guys taking the time to spend an hour with us. I think about that exactly again. And we'll keep you guys updated. Stay tuned. We're really excited about this and hope that the orders will come in shortly enough to be able to make this less dramatic as we go forward and set us up for a really strong year heading into next year. So I appreciate it. If you are in town, we are in Fremont, California, Silicon Valley, give us call, set something up, come by take a look at the facility. If you haven't seen our tools, they're very impressive and get a feel of the capacity because we have a lot of systems on the manufacturing line right now. So take care, and Happy New Year to everyone.

This concludes today's conference, and you may disconnect your lines at this time. Thank you for your participation.