Welcome to the Rambus Fireside Chat. My name is Mark Lepasas. I'm the Senior Semiconductor Analyst at Evercore ISI. So today, very happy to have Luke Serafin, who is the CEO, and Sumit Gagneja, who is the SVP and CFO. So Sumit, Luke, welcome, and thank you for joining us today. So, I think maybe if we could just start out with, Sumit, you're the recent, you're the new guy, right? What attracted you to Rambus, and what do you think as you have hit the ground?

Yeah, no, thanks, Mark. So, great question, and I'm glad to be here, super thrilled to be here. Rambus, as you know, we have three distinct business lines, product business, silicon IP business, and patent business, right, we generate a lot of cash. And we're right in the middle of this compute revolution or renaissance of CPUs, whatever you want to call it, right? And our products definitely play in there. We have great gross margins and we generate a lot of cash, right, that gives us ability to kind of invest back into the business and we'll talk about the capital allocation in a bit. So I look at that setup, you know, cycle of growth, very solid foundation, and my experience is in the semiconductor industry, right? I've been in the semiconductor industry for like 25 years, and especially my prior few roles very much into the data center, right? So I understand the data center market, the workloads being shifting from training to, you know, inference to agentech and all that sets it up. So that's what, you know, excites me a lot to be here.

Gotcha. Okay. All right. So, like, maybe if we just start out on that, you know, this higher level of view, like, you know, we talk to, you know, all the hyperscalers, and we get this idea that, you know, there's this demand for CPUs that's almost become insatiable, and they explain to us that as we've gone from training to inferencing, we go from one CPU to four or eight GPUs, going to inferencing one CPU to two GPUs, and then agentic could be one-to-one, or two CPUs to one, maybe even four or even higher. We hear those kinds of numbers. And I'm wondering, is that, you know, assuming that trajectory plays out, we're entering an agentic era, is there, I mean, is there any reason that you should not be participating in that, or your industry should not, you and your competitors, should not be participating in that industry as CPUs grow?

So we will participate to that growth or that renaissance, as you call it. What we've seen is that the AI market has expanded from AI training to inference, agentic AI. The initial AI training workloads required the GPU HBM type of architecture associated with very high performance CPUs. But the software workload that you have in AI training is very different than the type of software you have to run in agentic AI. The training has to do with building the models. Once the models are being built, then you have to use those models. And as you said earlier, you also need to actually call on other resources that already exist in the cloud to complete those models and run inference. So that creates that dynamic that you talked about, about the ratio between CPUs and GPUs changing in favor of CPUs. So this is a very strong underlying growth vector there. Now, you know, there's also tactical aspects, you know, associated with this. One is there's an insatiable need for more memory. And today the memory industry, you know, is in a supply tightness type of situation. So, people who build this infrastructure for agentic AI need to put their hands on memories, and there needs to be supplied of that memory. There's also the aspect of how fast the new CPU generations can roll out in the market, because, again, agentic AI requires a lot of the CPU capabilities, and these CPUs have to be available. So I think the underlying growth vector is very, very strong. I think that's going to put constraints on the memory market, constraints on the CPU market in terms of availability of products. But that's certainly a very strong tailwind for our business.

And you sell an RCD and you sell other chips that go onto the DIMM. Are all of these CPUs that we're talking about, will they all have DIMMs?

yeah for the vast majority of of the cpus they are dim based architecture because this is where you have the highest capacity you have the highest reliability as well and it's a it's a known architecture there's also a very large amount of uh you know software that has been developed you know for many many years on on this type of architecture that you know agentic ai for example is calling upon so you know the the all of these growth is going to create that demand for more dims the the dynamic that we see is this agentic AI is requiring more CPU power more core counts in the CPU and the more cores you have in the CPU the more memory channels you need to feed those CPUs so what you see in these CPU rollout is people are adding memory channels as they move from generation to generation and for each one of these memory channels we have the opportunity of adding one or two DIMMs depending on the workload that you know our customers work on so yes that will create a very strong demand for DIMM and our business is unit based it's the more DIMMs are shipping out the more revenue we have. It's more unit-based and ASP-based.

Gotcha. And can you describe the competitive environment right now? It seems like you may have missed the not done as well in the DDR4 cycle. It seems like you were first to market with DDR5. Is that fair? And then as part of that, can you also help us understand that there's different generations of DDR5 RCD chips and and how does that play into you know your your revenue trajectory and the competitive dynamics yes I'll start with

you know the DDR4 question you know we entered DDR4 we started from scratch and there were already you know established vendors there so we actually had to fight our share you know through those generation and and and you know at the end of the DDR4 generation of products, we could reach, you know, about 25% market share. The transition, the market transition from DDR4 to DDR5 allowed us to get almost a step function in terms of share, because we invested very early in the DDR5 chips. We engaged very early with the ecosystem partners, and that allowed us to secure a very strong footprint. And the footprint typically is what translates into market share going down the road. So although in the DDR4 generation of products we were at 25% share approximately, last year we ended up the year at 45% share in DDR5. So we established ourselves as the market leader in DDR5. And in DDR5 you have these multiple generations. We had in a very short period of time Gen 1, Gen 2, which is in production today, Gen 3 ramping in production, Gen 4, Gen 5, where we're shipping the early products. At every generation, it's the same type of challenges that we have to answer. We have, every generation has, you know, higher speed memories. So at every generation, memory suppliers have to re-qualify modules with new memories and a new RCD, mostly, because, you know, the speed has a direct impact on the RCD. The other chips on the modules, they can change at a lower cadence, but the RCD and the memory at every generation become faster and faster, and we have to re-qualify. And to re-qualify, again, we have to be first with very high-quality products engaging with our customers. So when we went from Gen 1 to Gen 2 in DDR5, we continued to increase share. Your Gen 3 is ramping in the market, and our footprint is very, very strong, as well as footprint in Gen 4 and Gen 5. So we'll measure share at the end of the year as we do typically. Now we have like three generations in play. But as we move on we continue to gain share and this has to come from the very fact that we engage very early with very high quality products. And if I come back to the history of Rambus, this is what we decided to do as a company. We actually stopped a lot of activities that were not central to this mission and we focused on that mission. And that was a good move, you know, in retrospect, because with AI, the market is accelerating. You know, we had to produce a new product every other year, you know, in DDR4. You know, in DDR5, we have to roll out a new product every year. And we have to roll out the companionships as well. So the focus that the company has had on that has been really a good thing for us.

And is, I guess the way I normally think about this is, Gen 3, is this, this is associated with Granite Rapids from Intel and Turin from AMD, is that right? And then what about Gen 4?

So Gen 4 is mostly ARM-based platforms from the CSPs. It's just an anomaly in the market, but it's ramping in the market and our footprint is also very, very strong there. But it just happens to be, you know, a large portion of the market is arm-based, you know, from, you know, from, from the CSPs.

Gotcha. And then, Gen 5, that should be Diamond Rapids and Venice, is that right? Correct. Yeah, that's correct. And those products, I think, the consensus view is that that's towards the end of this year, is that?

So, AMD announced, you know, that they were, you know, in production with, with Venice. But the chip being in production doesn't necessarily mean that the servers are in production. So, you know, the chip is in production. You know, we believe the first servers are going to show up really towards the end, you know, at the end of the year, the very end of the year. And then Intel announced that their Diamond Rapid is going to be, you know, next year. So it's a bit later than what we were hoping for, but there is definitely momentum there. Again, if we zoom out, the market is in demand for higher core counts and higher memory bandwidth. it and you know the venice platform and and the diamond rapid platforms offer that it's just you know the timing is a little you know further to the right that we were we were hoping for

and then how do we think about the asps of your of your rcd chips as you get higher speeds you get do you get higher asps also is that reasonable or do you deliver that extra for your customers

So, the pricing dynamic in this market is very interesting, and we often have the questions, you know, is it similar to the memory market, because our customers are memory vendors. Fortunately or unfortunately, it's towards anyone's judgment here, we are not going through the, you know, memory cycles. We provide a chip that is defined by JEDEC, it's defined by the industry, and our two competitors provide the exact same chip. So, no one of us, you know, would risk, you know, increasing, you know, pricing, because we would immediately lose share, you know, unless one of us is completely out of supply or has a major quality problem, then, you know, that would change the dynamic between the three. So, you know, there's not the big swings that you see on the server CPU market or on the memory market. We're more unit-based in terms of growth. What we see, however, is at every generation of product that we offer to the market, like when we move from Gen 3 to Gen 4, from Gen 4 to Gen 5, there's naturally an uptick in pricing. you know and then these things go to full production and this this optic in pricing decays over time so with that dynamic has always existed in in the market the good news is that with the acceleration of rollout of platforms I was talking about one platform every year now instead of one platform every other year we have more of these optics too you know and in aggregate you know we maintain you know our product margin you know between 60 and 65% whether the memory margins are 80% or whether they are negative you know we kind of stay

kind of more stable there. Gotcha okay now can you talk about where you are in the companion chip ramp so this is the idea where you along with the RCD you're selling maybe a power management temperature sensors a hub and and if I understand correctly this potentially doubles your content silicon dollar content if you if you get all of those is that the right way yeah that's correct it doubles the

silicon content if you move from a ddr4 module architecture to a ddr5 module module architecture when the industry moved to ddr5 they also moved some of the functions that were initially sitting on the motherboard onto the module that that's what happened that what explains the doubling of the of the time there and as you correctly say these chips that have moved from the motherboard to the module during that transition, the temperature sensors, the two of them, an SPD hub and a power management chip. When the market transitioned from DDR4 to DDR5, we put the emphasis as a company on the RCD because the RCD is the most complex chip on the module. And as we were growing share from 0% to 25%, we could not afford missing that transition. So it was very, very important for us to have that laser focus on the RCD transition. That explains why we went from 25% to 45%. The next most complex chip on that module is the PIMIC. And for the PIMIC, our strategy has been to develop that know-how internally. So silently over time, we've built our own team, our own IP, and we've introduced PIMIC, not in the first generation of DDR5, but in the follow-on generations. And this PIMIC, we have a steady growth of revenue. We're going to see that growth continue, especially as Gen 3 enters the market. Gen 5 is going to be another vector of growth on the PIMIC. And our strategy, because we were not coming first, was to actually develop the most complex PIMIC to leapfrog our competitors there, because people were asking, what are you guys doing in PIMIC? You've never had an experience there. So we leapfrogged with the most complex PIMIC, and we introduced the PIMIC in the most complex modules, and it's going to percolate down to the different modules. PIMIC represents half of that, doubling of the TAM, and the SPD hub and temperature sensor combine the other half.

And what kind of attach rates are you seeing on the latest generation right now?

It's difficult to say because we're still in qualification process, but our objective is exactly the same. Our objective is to be first with the latest product so that we maximize our footprint because our footprint just translates into market share. The other thing I would say about the PMIC as well is that as the modules become more and more complex and faster and faster, In the longer run, our customers are looking at suppliers that can supply the whole chipset because the interoperability between all of these chips is becoming more and more complex, and our customers expect us to work those interoperability questions before we actually supply the chips to them.

Gotcha. Vic, you know, we have a little bit of time left. I want you to talk about MR-DIMM. What is it and what's the opportunity? Where are we in the RAM?

So MR-DIMM is a way of increasing bandwidth and capacity using the same server architecture that you have today. So you have a processor, you have memory channels, and just imagine that you fully populate these memory channels, but you need more memory because you're hungry for memory. Then the only way to go out is to add another processor so that you have more memory channels. But that's not economically the best way to do this. So the idea is how do you use the same infrastructure, not add a processor, but double the capacity and double the bandwidth. And that's, you know, where the idea of MRDIMM came from. And on MRDIMM you have a module where you have memory on both sides of the module, and you have a mechanism with a chipset to multiplex the access to this memory, because processors have a higher potential on the bus in terms of speed than the memory have. So if you have a mechanism where you can use the full speed of the memory bus, but multiplexing the memory access on the module side, And all of a sudden, you have double the capacity and double the speed. Sorry for the technical stuff, but that's where it started. And it resolves a lot of problems because without changing the architecture, all of a sudden, you have all of these benefits. Now, in terms of timing, on the processor side, you need to have a memory controller that supports that function. And the platforms that support that function are actually Venice and uh diamond rapid so they are the platforms that are going to ramp in the market towards the end of the year and and next year uh the content on the module compared to a ddr5 module is four times 4x 4x so you had 2x from ddr4 to dr5 and 4x from a dim ddr5 to an mr ddr5 and 4x is because Because you have a more complex RCD on the chip, you have a more complex PMIC on the chip, so they are more expensive. You still have a hub, two temperature sensors, but you also have ten new chips that did not exist on the standard DIMM. We call data buffer chips that are here to do the multiplex between the memories. And if you take all that chips together, that's a content increase by a factor of four.

And are you of the view that you start seeing revenues from this at the end of this year?

very little you know because of the because of the ramp of the platforms you know we we do see revenue because we ship products to our customers and during their their their qualification but

we see there are more into 27 28 yeah and is the how would you describe the competitive environment for mr dim versus the the rcd business it's similar is that what we have today the only

thing i would say is that to the best of our knowledge today only you know renaissance and have the complete chipset, you know, Montage has not announced any power management chip for that.

Well, the red light is blinking, which means we ran out of time. Luke, Samit, thank you very much for joining us today and sharing your insights about Rambus.

Thank you, Mark.