Atomera Inc Q2 FY2023 Earnings Call

Hello, everyone, and welcome to Atomera’s Second Quarter Fiscal Year 2023 Update Call. I’d like to remind everyone that this call and webinar are being recorded, and a replay will be available on Atomera’s IR website for one year. I’m Mike Bishop with the Company’s Investor Relations. As in prior quarters, we are using Zoom, and we’ll follow a similar format with participants in a listen-only mode. We will open the call with prepared remarks from Scott Bibaud, Atomera’s President and CEO; and Frank Laurencio, Atomera’s CFO. Then we will open the call to questions. If you are joining by telephone, you may follow a slide presentation to accompany our remarks on the Events & Presentations section of our Investor Relations page on our website. Before we begin, I would like to remind everyone that during today’s call, we will make forward-looking statements. These forward-looking statements, whether in prepared remarks or during the Q&A session, are subject to inherent risks and uncertainties. These risks and uncertainties are detailed in the Risk Factors section of our filings with the Securities and Exchange Commission, specifically in the company’s annual report on Form 10-K filed with the SEC on February 15th, 2023. Except as otherwise required by Federal Securities laws, Atomera disclaims any obligation to update or make revisions to such forward-looking statements contained herein or elsewhere to reflect changes in expectations with regard to those events, conditions, and circumstances. Also, please note that during this call, we will be discussing non-GAAP financial measures as defined by SEC Regulation G. Reconciliations of these non-GAAP financial measures to the most directly comparable GAAP measures are included in today’s press release, which is posted on our website. Now, I would like to turn the call over to our President and CEO, Scott Bibaud. Go ahead, Scott.

Thanks, Mike. Good afternoon, everyone. Welcome to Atomera's second quarter 2023 update call. We had a great quarter, continuing to build strong relationships with our customers through performing wafer runs for those in Phase 3, executing on compelling new R&D, and building momentum with newer customers. I look forward to telling you about the developments. Capitalizing on the momentum generated by our first commercial license deal in Q2 with STMicro, we've been busy meeting with new and existing customers to emphasize the urgency of adopting and taking MST to production. We've made good progress, both with those semiconductor companies already in our engagement pipeline and generating interest from new customers. Efforts continue with our first JDA partner, and this quarter, we've been collaborating with them on the demonstration and testing of MST solutions for their particularly challenging applications. A lot of back and forth regarding those experiments has been taking place. We continue to engage with the central engineering unit for the purpose of bringing much-needed solutions to their business units with whom we are also speaking. We believe these steps bring us closer to signing a license with a BEU for a production project. Likewise, we continue to work with our second JDA customer on efforts focused on optimizing performance in their application, allowing us to initiate the milestone payments and associated licenses defined in the JDA agreement. Meetings with the JDA customer and our other licensees about the specifics of MST integration in their devices, our TCAD analysis, planning, executing wafer runs, and implementation of the results have been happening regularly and continue even today. A quick update on STMicro. We described the steps remaining for commercialization in detail last quarter. Shortly after ST signed a license agreement, work began using MSTcad CAD to create a new optimized design flow, integrating MST into ST's devices. As described before, ST and Atomera are cooperating closely to achieve the greatest possible performance and cost improvements using MST, with the primary design responsibility for this effort being ST, and Atomera in a supporting role. The first revenue milestone under the contract will be triggered when ST installs our technology on an epi deposition tool in one of their fabs. The TCAD work that's already begun will run in parallel with ST's manufacturing of MST wafers. The installation process is largely dependent on our epi tool vendor. Due to logistics delays on the tool modification, we are currently expecting this to happen early in the fourth quarter. Once installation is complete and ST has successfully dialed in the tool, they'll be ready to build MST wafers. When ST has completed their work, they will start wafer level qualification to create a high-volume, high-yield manufacturing process, which will trigger another milestone payment and grant them the right to manufacture and sell products incorporating Atomera's technology. At that point, ST will enter volume production and we can expect to start seeing royalty payments. Our announcement of the license agreement with ST has definitely made waves in the industry. We've had excellent meetings with a number of potential customers who design and build analog and power products and who are interested in working with us on MST. Some have already begun the process by commencing TCAD work with us, and we hope to add several new customers on this front in the near future. Work on RF-SOI continues to show very good promise in cellular handsets. Because of the large and expanding number of cellular frequency bands available in the world, the RF front end on mobile phones is becoming an increasingly complex and expensive piece of technology, which leverages advantages that specialized RF-SOI substrates can provide. However, those substrates also have some serious drawbacks related to open movement under the buried oxide layer. MST can help solve those problems by enabling lower cost and less complex front ends, which should provide an excellent market for Atomera's technology. We are working with a number of customers on this today and expect to work with more in the near future. I want to spend a little bit of time talking about how MST can provide a real benefit to smaller lithography nodes. One of the biggest challenges in semiconductors is to keep lowering power consumption as the nodes get smaller. A phenomenon that prevents them from doing so is called random dopant fluctuation or RDF, which are variations in the concentration of the implanted dopants, and the impact of those variations becomes more significant as the nodes get smaller. It's something that few people understand, increasing the cost and power consumption of advanced logic, DRAMs, and most other semiconductor devices. The good news is that MST is very adept at mitigating the problem of RDF. One of the most effective ways to improve power consumption is to lower the minimum voltage of transistors in each node. To do so, you have to manufacture each transistor with as little variation as possible. The more variation in your manufacturing process, the bigger the transistors you must design, and the harder it is to scale down your voltage. A significant driver of this variation is RDF. Thus, to successfully scale to lower voltages, RDF must be controlled. Our analysis shows that in the latest gate-all-around transistors, a single dopant atom diffusing into the channel can significantly alter the transistor's characteristics. This is why the dopant control characteristics of MST are so important for advanced node customers. A big focus of our R&D activities today is around proving this capability in the 2 to 4 nanometer range. In DRAMs, one of the most challenging limits on scaling is in the manufacturing margin of the critical circuits responsible for reading the memory bit, which are called sense amplifiers and typically make up 10% to 12% of the DRAM chip area. Since DRAM capacitors leak, the margin on these sense amplifiers defines how long the capacitor can leak before becoming unreadable, which establishes the refresh interval and resulting power consumption. By improving the variability of DRAM sense amplifiers, MST can help manufacturers make them smaller and utilize less power. In this chart, we show a 50% improvement of variability between matched transistors that use MST. Another way of looking at this is that an MST transistor can be a quarter of the size of a normal transistor at the same Sigma VT. Again, MST's ability to control random dopant fluctuation drives this significant improvement in variability. The growth of AI has led to applications that are dramatically more memory-intensive. These types of power consumption improvements for DRAMs are particularly important, which is why we're starting to see very strong interest from players within the memory segment for using MST. Atomera's world-class team of engineers and scientists continues to find ways of leveraging MST to advance the state-of-the-art in semiconductors. Recently, IEEE Spectrum featured a segment on Atomera's Founder and his efforts early in his career to bring another key material advance to market, the Erbium Doped Fiber Amplifier. That invention went on to become one of the foundational technologies enabling the Internet age. His technical leadership continues to drive our team to achieve similarly groundbreaking results for today's semiconductor industry. There's no doubt that Atomera is seeing wider interest across more applications than ever before. With our recent announcement of the ST licensing deal, we are seeing tangible proof that customers are standing up and taking notice, and we believe this will accelerate our time to revenue with more licensees. Although it has been difficult for us to provide much public insight into specific opportunities, I can tell you that the team is busier than ever. Our travel spending has doubled this year because we see promising opportunities with new and existing customers around every corner, and we're enthusiastic about closing them. With that, I'll ask Frank to now review our financials.

Thank you, Scott. At the close of the market today, we issued a press release announcing our results for the second quarter of 2023. This slide shows our summary financials. Our GAAP net loss for the three months ended June 30, 2023, was $5.2 million, or $0.21 per share, compared to a net loss of $4.5 million, or $0.20 per share, in the second quarter of 2022. In Q1 of 2023, our GAAP net loss was $5 million, or $0.21 per share. GAAP operating expenses were $5.4 million in Q2 of 2023, which was an increase of approximately $913,000 from $4.4 million of OpEx in Q2 2022. The biggest driver of the year-on-year increase was a $759,000 increase in R&D expenses, $423,000 of which was due to higher spending with our contract foundry, TSI Semiconductors, where we processed a substantially higher number of wafer lots than in recent years and we absorbed price increases for wafers and engineering services. The other main factor was payroll costs, which increased by $209,000 in Q2 2023, compared to the second quarter of last year, reflecting new hires that came on board last July. General and administrative expenses increased by $108,000, and sales and marketing increased by less than $50,000. Sequentially, our GAAP operating expenses increased by $192,000 from $5.2 million in Q1 of 2023 to $5.4 million in Q2, primarily due to a $156,000 increase in R&D expenses, also due to higher spending at TSI. Non-GAAP net loss in Q2 2023 was $4.3 million versus $3.6 million in Q2 of 2022 and $4.2 million in Q1 2023. The differences between GAAP and non-GAAP operating expenses in all the periods we've presented are almost entirely due to non-cash stock compensation expenses, which were $1 million in Q2 of 2023, $927,000 in Q1, and $859,000 in Q2 of 2022. Our balance of cash, cash equivalents, and short-term investments on June 30th, 2023, was $23.8 million, compared to $17.1 million on March 31, 2023. During Q2, we used $3.9 million of cash in operating activities, and we've raised $10.8 million in net proceeds from sales of approximately 1.4 million shares under our ATM facility at an average price of $8.15 per share. This compares to a very limited ATM activity in Q1. So we feel we are carefully balancing liquidity and dilution. As of June 30th, 2023, we had 25.8 million shares outstanding. Moving to our guidance, we still expect non-GAAP operating expenses for 2023 will be in the range of $16.25 million to $16.75 million. But likely, we'll be near the top end of that range, mainly due to higher spending with TSI. In April of this year, TSI increased its prices, while at the same time, their cycle times got substantially faster. We benefited from this through more cycles of learning, but the price increase and faster wafer processing, combined, increased our R&D expenses. Also, our travel to customers has snapped back to above pre-COVID levels, such that we expect nearly as much on travel in the first half of the year as we did in all of 2022. This is a welcome development because we're responding to greater customer interest, which should lead to additional licenses and faster commercialization. As Scott mentioned, we expect that ST will install MST in their tool in early Q4, which will trigger the first revenue milestone at that time. ST's commercial license is already influencing other major players to move more quickly to evaluate and install MST. Each commercial license involves upfront license fees with a list price over $3 million and results in recurring royalty revenue when the customer goes to production. So while our lack of revenue during the first half of the year is disappointing, in the big picture, we're confident that our investments in headcount, wafer processing, and sales activities are building the foundation for a profitable recurring revenue business. We do not give revenue guidance beyond the current quarter. So for Q3, we're guiding to zero revenue, though we may see some early recurring revenue from MSTcad licenses during this quarter. With that, I'll turn the call back over to Scott for a few summary remarks before we open up the call to questions.

Thanks, Frank. Once again, this quarter, the Atomera team has built strong relationships by working closely with customers to develop a deeper commitment to MST. We believe our large number of engagements are deep material and semiconductor expertise and the solutions MST provides to some of the industry's hardest problems will ultimately be rewarding to shareholders. I hope to share more successes on Atomera's part and announce more licenses and deals in the months ahead. Mike, we will now take questions.

Okay. Thank you, Scott. If you wish to ask a question, please click the Q&A button at the bottom of the Zoom window, then feel free to type in your question. I will do my best to aggregate the incoming queries and relay them to management. Alternatively, you can click the Raise Hand button, and we may call on you to ask your question live. And right now our first question comes from Richard Shannon of Craig Hallum. Richard, if you would kindly unmute, you may begin.

Great. Thanks, Mike. And Scott and Frank, thanks for taking my questions. I think the first one for Scott here just to start on STMicro. I appreciate the detail on the progress here, and I'm sure you're a little disappointed in the timing of the tool progress here. I guess my first question is, is there something very specific to STMicro, or is there an industry-wide issue? And what's your confidence in that being done by early fourth quarter?

Yeah, quick answer is, it is an industry-wide problem; it’s related to logistics issues that started in COVID and continue through today. Even in March, they've been working to pull this in. So there’s some chance that they could pull it in, but that's really not in their hands. It's their vendor, and they're trying very hard to get it accelerated. I think there's a chance it could happen in late Q3, but right now, our expectation is to be at the very beginning of Q4. And there's some chance that could move, but my belief is that all the urgency is there to get it done now. One thing I would like to point out, though, is that we're doing a lot of work with them today. So we're doing the development work that's necessary to happen in parallel with the wafers getting up and running. So, even though the installation has been delayed a bit, I'm not sure it has an impact on the overall schedule yet.

Okay. All right. That's fair enough to answer my follow-on there. My only other question related to STMicro, and I asked you this last quarter, obviously, with just hours or days after really engaging on your license with them. But maybe you got a sense of what the TAM for their smart power products looks like? I may be able to find any good answer to that in the last quarter. I'm wondering if you've got any more detail that help us frame that a little bit better?

I don't think we have anything new from what we provided in the last quarter, which is that the smart power resides in their analog sensor and MEMS group, which was about $1.1 billion, and therefore, about one-quarter of the total revenue for STMicro. But beyond that, we can't really provide any more granularity on the TAM.

Okay, let's discuss advanced nodes. I appreciate all the details provided in previous calls. It seems like activities are increasing. I specifically mentioned work on nodes between 2 nanometers and 4 nanometers. We are anticipating 2-nanometer and 3-nanometer developments, but there is a foundry that claims to have a 4-nanometer node. I'm not certain if it's genuinely at 4 nanometers or possibly 5, but an intersection with the 4-nanometer node could occur relatively soon. I don't want to raise expectations too high, but I’m curious about the progress and the potential timeline for working with advanced nodes. Could the 4-nanometer node be emerging in the near future? I'd like your perspective on that possibility.

Yes. So Richard, first, let me make a clarification. We're working on MST film implementations that would be in the range of 2 nanometers to 4 nanometers. Of course, anybody working on those very small nodes would want to be working with an MST film that is very, very thin like that. So my reference was not to a specific node like a 4-nanometer node or a 2-nanometer node, but to implementations that would be small enough to be appropriate in that kind of range of nodes. So, obviously, we haven't made any kind of guidance about thus being adopted by either an existing FinFET node or an upcoming gate-all-around node, but that's something that we're working very hard to achieve.

Thank you for the clarification. I'm glad I asked that question because I want that information to spread beyond this call. I have a couple more questions for Scott. In recent calls, and even over the past couple of years, you've been discussing the potential for RF-SOI. About 3 to 3.5 years ago, you mentioned engaging with customers who held a significant portion of the RF-SOI market. It seems like that engagement has expanded since then. Can you provide an update on what that percentage looks like today? I believe it was a majority even back then.

I think what I said back then was that we were working with the majority of the installed base of RF-SOI device manufacturers. That's still the case. I talked in this call about expanding that further. We have started working with more since I made that comment, and we continue to work with all the ones we are currently collaborating with. So yes, this continues to expand. As a matter of fact, we continue to make really good R&D progress in that area and partner with some important players in the RF-SOI space. So I'm very hopeful that this will turn into some licenses and revenue for us in the near future.

Okay. That's fair. Just one last quick question before I step back. Regarding DRAM, I know you've mentioned this previously, but your comments seem to indicate a stronger stance, particularly in light of AI developments. It appears that DRAM has been experiencing a slowdown. Could you describe whether your collaboration with DRAM manufacturers has intensified significantly over the past six months, especially considering that many of them have ample capacity available for testing? How would you assess the shift in your engagement with those manufacturers?

I definitely would say that's the case, Richard. We have been talking to DRAM manufacturers for years. We've had these variability results that I showed today. This is some new data, but we've had data in the past that showed we had good variability improvements. But I'm not sure if it's driven by AI because AI is absolutely driving the DRAM manufacturers to try to figure out how to solve some problems they can see the same demand coming there, and they're going to need solutions on power consumption and other things. But we certainly have seen an uptick in interest from our technologies in the DRAM space in the last six months. And so we're hopeful that leads to something positive.

Well, certainly it would be a big market for that were to happen. So it seems like there'll be a wholesale change if that were adopted even by one, so that would be very interesting to see. So, excellent. Well, I appreciate the time, guys. I will jump on the line. Thank you.

Okay. Thanks, Richard.

All right. Our next question comes from Cody Acree, The Benchmark. Cody, go ahead.

Thank you for taking my question. Scott, could you provide more details on the STMicro implementation and the delays you mentioned? Are these delays what you expected, or are they new developments this quarter?

No. I think when we announced the ST deal back in May, we said that they had to convert their tool. There are logistics issues due to parts that are long lead items and then just getting some people to do the actual work. At the time, we didn't know what date that was going to be scheduled. We were hopeful it could be scheduled sooner, but it looks like it's going to be a little bit longer than we hoped. It's not anything to do with our technology or ST's commitment or anything. This is just a case where you need some parts that are in short supply and are not going to be available for a little while.

Yeah, I mean, and I guess little bit of unique those delays, for the most part I guess, can you talk about what you're doing with subsequent engagements to make sure that you're streamlining the process?

Yes, this is a somewhat unique situation. Generally, people have Epi tools, and switching to support our technology requires only minor adjustments. They usually need to change a few gas spigots in the tool to run MST. However, in this case, there is an unusual tool setup that is more complex to modify quickly than what we typically encounter. I don't see this as a systemic issue, as we have previously completed conversions rapidly within weeks. In our Phoenix labs, we can accomplish a tool conversion in just a day or two. This is not a widespread problem. Can you also discuss the impact of the single atom dopant?

Yes.

That sounds like more of a newer issue that has come up.

Yes. So our analysis shows that in gate-all-around transistors, which are, as you know, going to be adopted by the foundries at very small process nodes, probably in the 3- and 2-nanometer level. Those transistors are highly doped in their source and drain regions. The challenge is that with random dopant fluctuation, some of those dopant atoms can move out into the channel. But in this case, the channel is so small that 1 or 2 atoms moving into the channel increases the concentration of dopants in that channel significantly, and they want the channel to be as clear of dopants as they can possibly make it. So, by implementing MST, which improves the chances that they won't see random dopants going into the channel, we can bring a big improvement in reliability from that perspective and performance.

And Frank, you talked about the engagement commitments that you're involved with. What is that plan for spending impact to your outlook?

Yes, like I said, we're not changing our full year guidance to be around the mid-$16 million range, which we gave at the beginning of the year. One of the things that we saw at the beginning of the year was there was a price increase that was imposed by TSI. We're sort of now used to that. We also had quite a number of lots that we're waiting in the queue because we have been talking about it in years past. At times, their cycle times were slow, and then there was contention with commercial business because of all of the constraints that existed in the supply chain. So during the first half of the year, we were able to clear a backlog of running wafers that we had been planning. I would say the first part of the year is really front-end loaded in terms of TSI spending. I didn't change our full year guidance because I think this will not revert back to the levels that they were in 2022 and before that because, at times, things were moving too slowly. We weren't processing enough wafers, but it's going to be more normalized for the year. So, yes, in terms of what's driving the headcount, some of it is the TSI costs, and we've added a couple of heads last year, and we still have open positions that are in our budget and are reflected in the full year guidance that we are looking to hire between now and the end of the year.

So if you have the personnel today, what do you think your spending could look like, or what's the optimal level of spending that you're looking for?

Well, I mean, the full year has us at about $4 million to $4.2 million a quarter. It's hard to say whether that's optimal because, as the business scales, it's likely that we would add additional headcount. But if you go back about 12 or 18 months, we were mentioning that we were feeling constrained in terms of human resources to do the work that we needed to support customers. I'd say we're still a little bit understaffed relative to the work that needs to be done, but it's not as severe as it was in the past. So I think we'll continue to provide annual guidance and the spending will increase, but I don't see anything happening at a step function rate. The TSI price increase does show, though, that in the big picture, we save a lot of money by not owning our own sort of mini-fab, which is a very prohibitive thing to do. But we rely on a number of vendors on the outside where we have to continually try to keep them honest because it does impact us if there are price increases in some of these providers.

And Scott, I guess, you mentioned the signing and the progress of STMicro encouraging others to move forward. Can you give us any color as to what that might have spurred? And are you also looking at greater engagement within STMicro and expansion of that engagement?

Yes, we've discussed this before. The partners we collaborate with possess strong technical expertise and carefully analyze our technology before making decisions. However, many of them are hesitant to be early adopters. When we approach a customer and mention our collaboration with STMicro, a respected company, it tends to prompt a serious response from them. After we announced our partnership with STMicro last quarter, we reached out to all our customers in the power and analog sectors and urged them to take this development seriously. This had a positive impact, and we have begun working with some of them, as I mentioned earlier. Additionally, it encourages others to recognize the necessity of getting involved as well.

And any expansion of the ST engagement?

Okay. Not that we can announce yet. ST has a number of different business units where our technology would be interesting outside of the one that we're working on. That's something that we'll hope to do with them over time, but we can't announce anything now.

All right. Thanks, guys. Appreciate it all. Okay. It looks like Richard Shannon has a follow-up question.

Yes, Thanks, Mike. Scott, just one quick follow-up for me. Supporting certain areas that you talked about initially like RF-SOI and obviously, power gets a little bit bigger or one thing. But when you talk about leading edge nodes in DRAM, you're talking about really large markets. How do things have to change from a headcount resource R&D wafer sort of view to make that reality, especially as you get close to that point in time where some sort of contractual license agreement would be signed?

Yes. If we hit on all of those simultaneously, I do think we'll have to expand headcount a little bit, but it may impact our R&D budget more than just on a headcount basis. One of the challenges we have in the market, especially for the most advanced nodes, is that the potential customers are used to working with equipment manufacturers like Applied Materials, ASM, or Tokyo Electron. When they come and talk about an improvement, they want to see a lot of data, wafers run to show the improvement. They use the same standard with us. The good news is we have our own epi tools, and we can do a lot of epi work to prove the technologies. The chart I showed earlier was actual silicon tested data, it's not simulation. We do a lot of simulation work and advanced work we can on the epi tool with lots of advanced metrology outside. But to be competitive, I think we'll have to take on more of that over time.

Okay.

But for the most part, I still feel very strongly in this engagement and in the business model we've established. We will be able to leverage a relatively small team and low expenses to create significant business opportunities, even with a slight increase.

Right. Okay. Perfect. That was my only follow-up question. That's all for me. Thank you, Scott.

Yes. If I could just continue on that, because I saw a question in the chat, and I thought it ties closely with what Richard was just asking. Someone was questioning, what do we run wafers for TSI? We've worked with TSI for over seven years. As Scott was saying, it's not always easy to build a complete device and test the benefits of MST on it. TSI gives us a cost-effective way to do that. We can prove out technologies like MSTSP and SPX for power devices and see the impact on the full device and have silicon data. It also helps to keep our epi tool calibrated. We want to run wafers periodically and see how devices run with MST over time. There are many benefits for our internal R&D work and trying to simulate in silicon what customers are doing. But in the future, as Scott alluded to, when you move to advanced geometries, it's harder for us to do in-house. Those are areas where, in the future, there could be costs. I alluded to that in the last earnings call that as we participate in advanced node ecosystems, those can be more expensive to outsource.

All right, Frank.

And Frank, there are several good questions that have come in on the Q&A chat. Let me mention a couple that you can answer relatively quickly. First is the expected quarterly cash burn going forward considering the increase in headcount and cost of wafer rents.

Yes, the guidance we provide is always based on non-GAAP operating expenses because we are not offering revenue projections beyond the current quarter. For the year, we expect those expenses to be between 16.25% and 16.75%, which translates to approximately $4 million to $4.25 million in non-GAAP operating expenses, closely aligning with cash on a quarterly basis. I stand by this expectation for the second half of the year.

And how much is left on the aftermarket facility?

Right. When we established the ATM facility, it was a $50 million facility. We started using it in the middle of 2022. We've done a total of $17.3 million on that. So, there's $32.7 million remaining on that after the end of last quarter.

Okay. We have a question about how the relationship with Arizona State University was established. Is there any additional information available regarding this, including whether other universities are being considered, and generally, how did this relationship develop?

This all began a few years ago, around 2017 or 2018, shortly after we went public. We needed more regular access to a 300-millimeter epi tool, but leasing it was very costly. The issue was that by the time we received the tool and got it calibrated, we often used almost all our lease time just preparing it for wafer runs. Then, when we had to lease it again, we faced the same challenges. We searched globally for options to buy a tool, but such tools are rare, needing a top-notch clean room and flexibility for leasing and installation. We have collaborated with numerous universities over the years, including UC Berkeley, Notre Dame, the University of Pennsylvania, Georgia Tech, and the University of Texas at Austin, alongside ASU, conducting research that connects us with many in the academic sector. We previously set up a 200-millimeter epi installation in Arizona and learned about ASU's facility, which led us to inquire about utilizing their resources. Over time, this relationship matured, and we were able to lease an epi tool at their site, which is beneficial for us. This facility has two chambers, one for 300 millimeters and another for 200 millimeters, allowing us to run both size wafers simultaneously and pursue advanced work for applications ranging from 2 nanometer to 4 nanometer. Our partnership with ASU has fostered a strong connection, and we are engaging in research initiatives together. The collaborations we have with ASU also involve our customers, who participate in various projects with us, making it an overall positive and productive relationship.

All right. Thanks. And outside of ST and the JDAs, looking at the engagement pipeline that we publish, the comment here is that there hasn't been any movement in the pipeline. Can you provide a bit more detail as to potentially moving customers along the pipeline and the level of activity there?

I understand your frustration with that. During the COVID period, we experienced a slowdown; there were many activities, but not many people progressed through the phases. We're becoming more active with existing and new customers, and I believe we'll start to see pipeline growth soon. Phase 1, which is at the start of the funnel, requires customers to have signed an NDA with us, a step that can sometimes be a significant obstacle. They also need to be planning a wafer run with us. Occasionally, we remove individuals from Phase 1 if they've had discussions with us but become less active. Yet, we always strive to enhance the quality of participants in this phase. I anticipate more growth in this area shortly. However, my primary focus is on encouraging those in the later stages to progress into Stage 4 and ideally into Stage 5. We will continue to prioritize this effort over merely increasing the numbers in the pipeline.

And of course, there's more requests for detail on the JDA relationships. I wanted to see if there was any additional commentary you can make about JDA 1 and moving toward their business units.

Yeah. I saw this question about JDA 1 regarding discussions with the Central Engineering group versus the Business units, and I want to emphasize that we speak with both. We talk with the guys in the business unit to understand their challenges with their process nodes, what they're trying to achieve in the market. Many times, they will give us guidance on what they need to work on. We perform simulations and experiments based on their feedback. We then share the results with them, and they decide on the next steps. This has been happening continuously. It's a dialogue between us, the central engineering group, and the business units. In terms of roles, the business units are the ones identifying what they truly need, while the central engineering groups administer the relationship by setting up experiments, testing, and reviewing results with us. I know it's frustrating that you can't see tangible outcomes, but we have been continuously working on these tests and experiments. The only bad indicator would be if we stopped being asked to do experiments. As long as they continue to solicit our assistance, we're pursuing valuable opportunities.

Okay. And one final question here before we adjourn. We announced a license with a foundry partner a while back, and the last update indicated that they were waiting for the second run data. Wondering if you could provide an update on that.

Yeah. We don't have that data yet. I don't think I'm in a position to provide schedules on that, but I can tell you that we have looked at the results from the first run and have been working with them on defining a next run. We have a compelling plan that we hope to see results from soon.

Okay. And I think that wraps up the questions here. So I'll turn it back to you, Scott, for closing comments.

All right. Thanks, Mike. I want to thank everyone for attending today's presentation. I'm happy we're able to share with you some of our recent progress and our potential in some new technology areas. Please continue to look for news, articles, and blog posts to keep you up-to-date on our progress, which are available along with investor alerts on our website, atomera.com. We are planning to attend a number of investor conferences in the coming months, so please look out for those announcements as well. Should you have any additional questions, please contact Mike Bishop, who’ll be happy to follow up. Thanks again for your support, and we look forward to our next update call.

Thank you. This concludes the Atomera webinar.