Hello, everyone, and welcome to Atomera's Fourth Quarter and Fiscal Year 2025 Update Call. I'd like to remind everyone that this call and webinar are being recorded and a replay will be available on Atomera's IR website for 1 year. I'm Mike Bishop with the company's Investor Relations. As in prior quarters, we are using Zoom, and we will follow a similar presentation format with participants in a listen-only mode. We will open with prepared remarks from Scott Bibaud, Atomera's President and CEO; and Francis Laurencio, Atomera's CFO. Then we will open the call to questions. If you are joining by telephone, you may follow a slide presentation to accompany our remarks on the Events and Presentations section of our Investor Relations page on our website. Before we begin, I'd like to remind everyone that during today's call, we will make forward-looking statements. These forward-looking statements, whether in prepared remarks or during the Q&A session, are subject to inherent risks and uncertainties. These risks and uncertainties are detailed in the Risk Factors section of our filings with the Securities and Exchange Commission specifically in the company's annual report on Form 10-K filed with the SEC on March 4, 2025. Except as otherwise required by federal securities laws, Atomera disclaims any obligation to update or make revisions to such forward-looking statements contained herein or elsewhere to reflect changes in expectations with regards to those events, conditions and circumstances. Also, please note that during this call, we will be discussing non-GAAP financial measures as defined by SEC Regulation G. Reconciliations of these non-GAAP financial measures to the most directly comparable GAAP measures are included in today's press release, which is posted on our website. Now I would like to turn the call over to our President and CEO, Scott Bibaud. Go ahead, Scott.

Thanks, Mike, and good afternoon to everyone. In Atomera's fourth quarter, we made great progress moving existing customers forward in our targeted segment, achieving very strong technical advantages, commencing new customer engagements in nontraditional areas and made our first foray into the world of government-funded collaborative developments, all positioning us strongly for commercial execution in 2026. Today, I will give you an update on all of our activities as we set the table for our business prospects in the new year. Technology news recently has been dominated by the rapid advancement of artificial intelligence and the associated semiconductor challenges that AI entails from the allocation of limited GBU supply, the enormous stresses put on our energy infrastructure and the associated surge in memory prices. Atomera's technology is positioned to assist with each of these industry issues as we deliver materials, which help to relieve each pain point. So let me start off with our recent exciting progress on Gate-All-Around transistor technology, which is the foundational architecture used in AI GPUs, CPUs and bleeding edge network components. The challenges with manufacturing these next-generation transistor devices at 2-nanometer and below are widespread and a concerted effort by the full ecosystem of industry players is required to manufacture them at scale with economically viable throughput and yield. This has been the focus of our recently announced strategic partnership with a large equipment OEM. Target customers are TSMC, Samsung and Intel, who are in production and a new Japanese manufacturer, which is deep in development. Atomera's MST technology delivers some very compelling solutions in this space, in particular, for diffusion blocking. These tiny Gate-All-Around transistors require extremely high phosphorotoping levels constrained to a very small area in the source and drain of the nanosheet. Under the intense semiconductor manufacturing environment, it's difficult to keep these dopant atoms in their proper positions and just a small amount of migration into the channel can severely impact performance, efficiency and yield. Atomera's MST is uniquely well suited to hold these roving phosphorus atoms in place. Although this MST characteristic is well proven in older technologies, implementing MST in devices that are around 2 nanometers, while maintaining its efficacy is something that industry players insist must be validated on silicon at real world scale, and we've been working hard to do so. Our target customers have been looking into two results to prove high-volume manufacturability. First, that MST can be effectively deposited into the actual nanosheet structure. And second, that the diffusion blocking characteristics are better than other methods the industry is currently evaluating or using. Obtaining these results is not straightforward and requires access to advanced structures that are generally not available, are very expensive, and frequently proprietary. But we've been able to make steady progress with the help of a Gate-All-Around customer and our strategic partner. Just in the last month, we obtained very exciting silicon results in both targeted areas, which we believe provides the definitive proof to drive adoption of MST at all four of the world's Gate-All-Around customers in the future. Not only can MST be deposited into those structures using existing tools and standard gases, but it is a far superior diffusion blocking material than those currently used by the industry. We anticipate that we will be able to implement this technology with leading industry players over the next few quarters. Of course, we're quite excited by these recent results since our advanced node, our Gate-All-Around business segment has extremely high revenue potential. But we're also making convincing progress in our other customer areas, so let me provide a short update there. In DRAM, the technology road map is at a key inflection point as DRAM finally follows other logic and memory architectures in making better use of the vertical dimension. We are getting involved in offerings to enhance the performance of next-generation architectures in addition to solutions for products currently in production by the major memory suppliers. During the last few months, we have had two major solution offerings that we're working hard to validate since their market potential is very high. Notably, these are both wafer-based solutions, which are easier to adopt and test, avoiding many of the integration complexities required in some of our other applications. And with the current robust market for memories, we believe our potential customers will have a generous R&D budget to pursue these ideas. Atomera is currently conducting many wafer runs with our various customers. Most of these are processing through their fabs, so we will expect more information soon. One customer has just gotten preliminary results, which look promising. But we will get a better view when the final data is available in about a month. If the results look good, we'll be pushing for a joint development agreement and a license to advance this technology to production. In the RF-SOI space, our offering is very strong, considering that it can provide performance improvements for multiple important areas, including for the RF switch and the low-noise amplifier. Because we are working with so many of the key players in this industry, including foundry and fabless suppliers, we hope to drive adoption broadly. Again, in this space, our solution can be implemented with a wafer-based solution, meaning our customers can choose to deposit it on wafers themselves before starting their full manufacturing process, or they can even buy RF-SOI MST wafers from a third-party supplier. Our license structure supports both of these approaches. In power, we are working with some very large players to ultimately be incorporated into their product offerings. Although we had a setback with ST last year, we continue to work with them on MST solutions across multiple business units. In addition to our traditional BCD business opportunities, this quarter, we had several other inbound interests emerge for power applications. Through our own internal analysis and modeling, we have uncovered an opportunity for MST entrench bets, which are an important component in optimizing energy efficiency in AI data centers. Our simulation shows the potential for MST to improve performance by more than 40%. We got this result after Christmas and already have a customer interested in kicking off development. Similarly, using our MST simulation capability, we have demonstrated how MST can improve HBT devices, which are high-speed transistors frequently used for amplifying and switching signals in RF communication systems. Discussions are underway with a potential first customer in this application as well. In GaN, I'm happy to report that our first commercial customer has now started running wafers for GaN on silicon with MST technology. For many reasons, this is exciting. This large customer can grow their own GaN wafers and manufacture electrical devices on them, which means they can move even faster than our in-house work with Sandia National Labs in Texas State. So we expect that we will actually move ahead of our own internal development efforts over the next few quarters. Second, they are exploring GaN in both RF and power technologies. These independent efforts by multiple industry and scientific partners frequently can accelerate time to revenue, which is what we're hoping to accomplish. Last month, we announced that our GaN on Silicon concept paper had been approved to move to the proposal stage for a project with Power America to advance the state-of-the-art and wideband GaN materials. We announced this for a variety of reasons. First, we wanted to show the widespread interest from customers, the science community, and industrial organizations for an MST solution for GaN on Silicon. Indeed, we've already received several letters of support from multiple future customers showing interest in this solution. Second, this concept paper was our first application for outside development funding. And although the funds sought for this first effort are modest, they put us in the pathway for a variety of future material development funding opportunities, which can provide us assistance going down the path we are planning to travel anyway. By engaging in these joint development opportunities, we are promoting our technology, receiving financial assistance, and assuring a customer base all in one project. To summarize, the past few months have been an incredibly productive time in terms of technical development and the buildup of a variety of new customer opportunities that I believe will lead to business deal announcements later this year. Finally, as we close out 2025, let me give you a few thoughts on our accomplishments. Last year, we took our early development and simulation results on Gate-All-Around and converted it into what I now believe is our greatest company opportunity. We did that through working with a lead customer and with a strategic partner who is also a major equipment OEM. This is a significant departure from how we've approached the market in the past. The industry has a long history of relying on this OEM to deliver material solutions for their problems. So we truly believe that their influence will help us to convert our recent strong technical results to licenses and revenue. We made technical breakthroughs in our other core markets to enable applications like LNA for RF-SOI, a new architecture for BCD and next-gen DRAM solutions. Using AI, our development team has gotten better results more efficiently than ever before. We kicked off a record number of wafer runs with leading customers, initiated several new projects, and solidified the business talent on our team, which should lead to further contract announcements over the course of this year. And much of this work was done, emphasizing wafer-based products, which we believe will result in faster time to revenue. In short, 2025 efforts have set us up well for commercial announcements later this year. With that, I'll turn the call over to Frank to review our financials.

Thank you, Scott. At the close of the market today, we issued a press release announcing our fourth quarter and full year results for 2025. This slide shows our summary financials. Revenue in 2025 was $65,000 and consisted of NRE fees for wafer deliveries and MST CAD licensing. Our GAAP net loss for the year ended December 31, 2025, was $20.2 million or $0.65 per share, compared to a net loss of $18.4 million or $0.68 per share in 2024. On a non-GAAP basis, 2025 net loss was $16.1 million or $0.52 per share, while 2024 net loss was $15.4 million or $0.57 per share. GAAP operating expenses were $20.9 million in 2025, reflecting an increase of about $1.5 million from $19.3 million in 2024. The main contributor to the rise in GAAP operating expense was a $1.1 million increase in stock compensation expense due to changes in our executive equity-based compensation. In Q1 2025, we implemented PSUs for executives that vest based on our stock price performance relative to the Russell 2000 Index. These PSUs vest over three years, compared to the four-year vesting for options and time-based RSUs granted to executives in previous years. Despite the shorter vesting period, executives vest in PSUs based solely on stock price performance. Aside from stock compensation expense, the drivers of GAAP and non-GAAP expenses are largely the same. Thus, my remaining comments will focus solely on non-GAAP results. Please refer to the slide presentation for a reconciliation between GAAP and non-GAAP expenses. Total operating expenses in 2025 amounted to $15.9 million, up $429,000 from $15.4 million in 2024. R&D expenses increased by $794,000 from $9.4 million in 2024 to $10.2 million in 2025, mainly due to a $676,000 increase in outsourced engineering as we utilized various new device fabrication vendors to replace TSI semiconductor. G&A expenses fell by $272,000 from $5.1 million to $4.8 million, due in part to a $421,000 decrease in compensation expense, which was partially offset by a $118,000 increase in professional fees for legal, IP, and audit services. Sales and marketing expenses decreased by $94,000, affected by a lower headcount, though some recruiting fees offset this reduction. Company-wide, our compensation expense, again on a non-GAAP basis and excluding stock compensation, decreased by $582,000 in 2025 compared to 2024. This reduction reflects our Board's pay-for-performance discipline. Despite achieving key technical milestones in 2025, the Compensation Committee concluded that the full executive bonus payout was not warranted based on the commercial progress made during the year; therefore, the committee withheld approximately $669,000 in executive bonus compensation impacting the entire executive team. The withheld amount may be earned in 2026 if we meet specified commercial objectives. Regarding our quarterly results, the non-GAAP net loss for Q4 2025 was $3.3 million or $0.10 per share, compared to a net loss of $4.4 million or $0.14 per share in Q3 and a net loss of $3.9 million or $0.14 per share in Q4 2024. Non-GAAP operating expenses dropped by $1.1 million to $3.2 million in Q4, primarily due to a reversal of our bonus accrual that took place in Q4. Our cash, cash equivalents, and short-term investments on December 31 totaled $19.2 million, down from $26.7 million at the end of 2024 and $20.3 million at the end of Q3 2024. We used $14.9 million of cash in operating activities throughout 2025, with $3.2 million used in Q4. During 2025, we sold around 1.6 million shares under our ATM facility at an average price of $5.15, generating net proceeds of about $7.6 million after commissions and offering expenses. As of December 31, 2025, we had 32.4 million shares outstanding. After year-end, we raised an additional $3.2 million in net proceeds by selling approximately 1.3 million shares at an average price of $2.47. For Q1, we anticipate recognizing revenue between $50,000 to $100,000 from MST wafer shipments to customers. As per our usual practice, we will not provide revenue guidance beyond this quarter. Our 2025 non-GAAP operating expense was $15.9 million, which is significantly lower than the guidance range I provided last quarter, primarily due to reversing $669,000 of accrued bonuses. In 2026, we will continue to aggressively manage costs, limiting our expense growth to areas directly linked to revenue and immediate commercial progress. The planned increases mainly pertain to hiring two senior go-to-market leaders: our VP of Sales, who joined in October, and a new Head of Marketing who will follow. The comparison of our planned expenditures for 2026 against 2025 may appear distorted due to the potential payout of the executive bonuses withheld from 2025, as this amount will need to be accrued alongside the 2026 bonus. Consequently, we expect our non-GAAP operating expense to be about $18.5 million in 2026. While this represents a 17% increase on paper, when adjusted for the timing of the executive bonus accrual, it is more in the realm of 8%. It is also important to note that earning back deferred executive bonuses and securing the 2026 bonus will necessitate our adherence to aggressive, commercially-focused milestones.

Thank you, Frank. The entire focus of our efforts in 2025 is getting to commercial agreements. The work we've done up to now has positioned us well to close on those opportunities and I look forward to sharing our successes with you as the year progresses. Mike, we will now take questions.

And right now our first question comes from Richard Shannon of Craig-Hallum. Richard, go ahead.

Great, Mike. Can you hear me?

Yes. Yes, we can.

I'm at the airport and there’s a bit of noise, so I apologize for that. I don't have much time before I need to catch my flight, but I have a few questions. Scott, you made some interesting comments about Gate-All-Around. If I understood you correctly, you mentioned expecting significant next steps in the coming quarters. Typically, you've been cautious about providing specific timelines for major milestones, but it sounds like you're more confident now. Could you elaborate on this confidence and explain why you feel that way?

Yes, I can share this slide to answer your question, Richard.

Please do.

On the right-hand side, you can see where MST is deposited around the source and drain structures. That is a very challenging task. We've been discussing with our Gate-All-Around customers the use of MST to prevent dopant diffusion. One of the major issues is that phosphorus can penetrate these channels, which can only accommodate a few phosphorus atoms before they start to significantly degrade, impacting yield and performance. Our customers have acknowledged the potential of MST to block phosphorus but were concerned about whether we can deposit it in such tiny structures, which are just 2 nanometers wide. For perspective, it takes about 100,000 nanometers to equal the width of a human hair. We had to demonstrate that we could deposit MST with high quality in these small areas, and we have achieved that. The second concern was whether that thin layer of MST effectively blocks phosphorus in such a limited space. They are currently using a different method that is not very effective, so we needed to prove that our solution works better. The answer is yes, and we have recently received test data to validate that. It’s still early, and we haven’t reached out to all of our Gate-All-Around customers yet, but we believe our strategic partnership will facilitate discussions, and they will want to start testing our solution right away. This is why I feel much more confident now. We haven't been this excited about technology results at the company in a long time.

Okay. Great deal. I'm sure I'll follow up a little bit on that one. The second question is, you mentioned two things you have to prove: that you are better than alternative solutions. We haven't really heard you talk about what other potential customers are considering. Can you describe what those are, whether they're internal developments or something from other research organizations, and to what degree you have visibility into how well those are doing as well?

Yes. We’re not really discussing a range of other technologies. The industry has previously utilized silicon arsenic, which is effective for placing a spacer between the phosphorus and the channel, but it fails to effectively prevent dopant diffusion. We have conducted extensive testing of our MST technology against silicon arsenic and demonstrated significantly better diffusion blocking results. Additionally, the industry typically prefers to avoid using arsenic in its manufacturing processes due to its cost and potential dangers. Therefore, providing a solution that eliminates the need for that material is likely viewed positively by the industry.

Okay. Fair enough. Very interesting here. My last question before I need to leave, Scott, is regarding the number of inbound calls you're receiving in the power sector, which I know you have been promoting for some time. STMicro was also focused on this area before its setback. You mentioned that a few years ago, you characterized the RF-SOI space as having significant coverage, with more than half of the market share. Can you provide any insight into how much of the power space you are currently covering with all these new companies that are approaching you? Any way you would describe that?

It's a bit more challenging in the power segment since it's a much larger and more diverse market. While we have a strong presence in RF-SOI, where we feel confident we’re collaborating with most of the key companies, the power market is different. We have engaged with leaders in areas like TrenchFET and HBT, and we're actively working with various companies in this space. However, I can't definitively say that we’re working with the majority of them in power.

I wasn't expecting most of it, but since the power space is quite large, I thought that even having 10% or 20% would provide good coverage. I appreciate your perspective on it. I have to step out now, Scott.

All right. Thank you, Richard.

Thank you, Richard. We have some questions coming in on the Q&A line. However, I will begin with one. Scott, can you provide an update on the progress of your Vice President of Sales, Wei?

Sure. Wei joined in October, and he's been getting up to speed and proving to be very helpful. I'm really enthusiastic about having someone who is pushing the team as hard as he is on the sales front. He's not only focusing on our current customers and assisting us in acquiring new ones, but he's also leveraging several past relationships to bring them on board, allowing us to connect with customers from a different perspective. This has been very positive, so overall, I'm pleased with his progress so far.

Great. And a number of questions about wafer activity at the fab. And as it relates to general activity level, how would you characterize that?

Yes. So I think just starting earlier in the middle of 2025, we started to get a lot of customers coming in with wafer run simultaneously, which is quite busy for us to get them into our fab and deposit MST on a very high-quality basis and they get it back out, so they can start running the wafers. Today, we're still running things in our own fab, but for the most part, we've shipped out a lot of that stuff out to our customers. And now we're kind of in a waiting game, it takes 6 to 9 months for customers to run their wafers once we send them back to them and then get the test results, and then we'll review those and we'll figure out the next steps from there. But we really feel confident that what we have done in these runs is good stuff. We use MST CAD simulation software to figure out what we expect the outcome of these runs to be and we're really hopeful that our TCAD has been accurate. And if we get the results that we hope for, that our customers want to move forward into a productization effort.

Okay. And generally speaking, I have a question here, and I think we've covered it on prior calls, but can you describe why selling blank wafers makes it easier to go to market?

Yes, absolutely. I just showed a graphic of a Gate-All-Around device, which is quite difficult to integrate. When we attempt to integrate into that device, the customer starts with a bare wafer and builds up various structures. At some point, they create a hole in those structures and request us to insert our MST. We then need to determine how to fill around it, which affects all the surrounding layers. This process is called integration engineering, and it's quite challenging. However, for many of our applications, we refer to wafer-based products, where the customer buys a blank wafer and immediately applies MST on it. They then begin their processing on top of that, which allows us to avoid the complex integration issues we encounter when MST is deposited in the middle. Today, I discussed some applications we are exploring for DRAM that involve wafer-based products, which we will provide to customers. While we won't be manufacturing wafers ourselves, we will offer solutions that can be directly applied to them. Additionally, for RF-SOI and our gallium nitride products, we also have wafer-based solutions. We're enthusiastic about these because they are easier to integrate, leading to a faster time to revenue.

Okay. Great. Here's another one. Can you please explain more about power saving in AI than how MST can help achieve that?

Yes. So it's a lot of ways. I just showed you the Gate-All-Around transistor. So fundamentally, in semiconductor manufacturing like that, if you can bring a performance improvement, you could also probably trade that off to get lower power if you chose to do so. So that's one way. Another way is with our power solutions like on our BCD products or our TrenchFET products or our GaN products. Those are targeted for the type of electronics that will be developed that go into AI data center to help lower the power in the racks. So I'll give you one industry dynamics that we're tracking in AI data centers. They have historically used a 12-volt power supply on the rack. But recently, the industry is moving away from 12 volts and they're moving to 48 volts because 48 volts is 4x more efficient at saving power when you're providing power to the racks for all of those servers. The 48-volt power supplies use a lot of TrenchFET devices. That's the primary device that they use in there. And so we are trying to offer solutions for TrenchFET, so we can help to address that. The other thing is gallium nitride obviously, a very power-efficient device. Those of you who have the small power supplies that go into your backpack or suitcase like they weren't able to do before you understand that those are much more efficient, and that's why we're trying to engage in gallium nitride.

Interesting. Thank you. Okay. Can you give us an update on your JDA1 and JDA 2?

Yes. I need to be cautious not to share too much about what JDA 1 is working on. However, we continue to collaborate with JDA 1, and I am optimistic that the technologies I mentioned today will help accelerate their progress towards a production development effort that has been anticipated for a while. JDA 2 is one of our customers currently producing wafers with us. I can't provide too many specifics about their current status, but they are indeed producing wafers.

Great. And going back to the Gate-All-Around, is MST being evaluated at the customer's fab at this point?

Yes, we are currently collaborating with one customer in the Gate-All-Around sector who has been instrumental in our efforts. When I discussed the structure and the need to perform deposits within it, it became clear that access to the wafers is essential for testing those structures. The positive development is that we are working with one potential Gate-All-Around customer to assess MST at this time. I hope to engage with all four customers in the future.

Okay. And when do you expect an evaluation to be completed of the wafers?

For Gate-All-Around or?

Yes. For Gate-All-Around.

For Gate-All-Around, it's difficult to determine precisely with some of the customers during our visits to present the data we have. We believe our data is compelling enough that they might not even need us to perform deposition inside their Gate-All-Around structure since we have already demonstrated our capabilities. Our goal would be to persuade these customers to install MST in their fabs and have their R&D teams begin implementation. The speed of this process is uncertain, but I can say the team working on Gate-All-Around is moving quickly, and if they choose to adopt it, they will push us harder than we have ever been pushed by a customer before.

Okay. Great. And just one last question here is on how MST can help or improve quantum computing.

It's interesting. That's something we're currently addressing. I can't go into detail about how our MST technology will relate to quantum, but I can tell you we're putting in a lot of effort in this area. Previously, we had a theory regarding MST's potential to enhance the purity and availability of Silicon-28 at a lower cost, which is essential for quantum wells. However, that did not materialize. Therefore, we are exploring other technologies right now, and I hope to share more with you later this year.

And Scott, you can proceed with any closing comments.

Thank you all for joining us to hear about the progress being made here at Atomera. Please continue to look for our news, articles, and blog posts, which are available along with investor alerts on our website atomera.com. If you have any further questions, feel free to contact Mike Bishop, who would be happy to follow up. Thank you again for your support, and we look forward to our next update call.

Thank you. This concludes the Atomera Fourth Quarter Conference call.