Ladies and gentlemen, good afternoon. At this time, I would like to welcome everyone to QuickLogic Corporation's Second Quarter Fiscal 2025 Earnings Results Conference Call. As a reminder, today's call is being recorded for replay purposes through August 19, 2025. I would now like to turn the conference over to Ms. Alison Ziegler of Darrow Associates. Ms. Ziegler, please go ahead.

Thank you, operator, and thanks to all of you for joining us. Our speakers today are Brian Faith, President and Chief Executive Officer; and Elias Nader, Senior Vice President and Chief Financial Officer. As a reminder, some of the comments QuickLogic makes today are forward-looking statements that involve risks and uncertainties, including, but not limited to, statements regarding our future profitability and cash flows, expectations regarding our future business and statements regarding the timing, milestones and payments related to our government contracts and statements regarding our ability to successfully exit SensiML. Actual results may differ due to a variety of factors, including delays in the market acceptance of the company's new products, the ability to convert design opportunities into customer revenue, our ability to replace revenue from end-of-life products, the level and timing of customer design activity, the market acceptance of our customers' products, the risk that new orders may not result in future revenue, our ability to introduce and produce new products based on advanced wafer technology on a timely basis, our ability to adequately market the low-power competitive pricing and short time to market of our new products, intense competition by competitors, our ability to hire and retain qualified personnel, changes in product demand or supply, general economic conditions, political events, international trade disputes, natural disasters and other business interruptions that could disrupt supply or delivery of or demand for the company's products and changes in tax rates and exposure to additional tax liabilities. For more detailed discussions on the risks, uncertainties and assumptions that could result in these differences, please refer to the risk factors discussed in QuickLogic's most recently filed periodic reports with the SEC. QuickLogic assumes no obligation to update any forward-looking statements or information, which speak as of the respective dates of any new information or future events. In today's call, we will be reporting non-GAAP financial measures. You may refer to the earnings release we issued today for a detailed reconciliation of our GAAP to non-GAAP results and other financial statements. We have also posted an updated financial table on our IR web page that provides current and historical non-GAAP data. Please note, QuickLogic uses its website, the company blog, corporate Twitter account, Facebook page and LinkedIn page as channels of distribution of information about its business. Such information may be deemed material information, and QuickLogic may use these channels to comply with its disclosure obligations under Regulation FD. A copy of the prepared remarks made on today's call will be posted on QuickLogic's IR web page shortly after the conclusion of today's earnings call. I'd now like to turn the call over to Brian. Go ahead, Brian.

Thank you, Alison, and good afternoon. Since our last conference call, we have focused considerable engineering resources towards two strategic initiatives that we will discuss today. We strongly believe these initiatives will accelerate storefront design wins for our strategic rad-hard FPGA and expand our served available market to include very high-density eFPGA hard IP designs targeting advanced fabrication nodes and eFPGA designs that require certain advanced capabilities. This allocation of engineering resources has pushed deliverables and associated revenue recognition forward for several contracts. This has decreased our revenue outlook for Q3, but it is expected to fuel a substantial increase in Q4 revenue. Now let's discuss what drove us to make these decisions and the opportunities we expect them to enable beginning in Q4. It has been well publicized that the DoD has prioritized certain strategic defense systems, including Golden Dome. As a result, U.S.-based defense contractors have accelerated the development of the associated programs. Many of these programs will require radiation-tolerant and in some cases, strategic radiation-hardened semiconductor devices that are fabricated in the U.S. Due to this, we took steps to ensure we are ready to support this accelerated development. After working nights and weekends, our engineering team delivered design files on Sunday to GlobalFoundries to fabricate a strategic rad-hard or SRH FPGA test chip using its 12LP fabrication node. This initiative was financed by QuickLogic and is independent from our contract with the U.S. government. Our decision to invest the money and resources to develop this test chip now is based on our belief that it is critical to helping us secure strategic design wins and accelerate our storefront business model. We have been discussing this initiative with certain large DIBs for a couple of years who have programs in development today that are good candidates for an SRH FPGA. We have designed the test chip to meet their requirements. To ensure we are ready to leverage this opportunity and our accelerated introduction of Australis 2.0, which I'll discuss in a moment, we raised money in June and early July with our established ATM. We anticipate ROI from our SRH FPGA test chip initiative beginning in 2026. And if we are successful in winning designs, we believe storefront production contracts could be worth hundreds of millions of dollars in the coming years. When we initiated our work to develop an SRH FPGA test chip, we believed certain DIBs would be ready to evaluate it in early 2026. However, during a conversation within the last week with one of the large DIBs, I was advised they would like access to the test chip as soon as possible and told me the test chip as it is defined may satisfy their program requirements. I know from speaking with investors at conferences and by phone that many of you are focused on the phenomenal growth potential of our storefront business model. I couldn't agree more, and I can assure you that I am intensely focused on executing the prerequisites needed to realize this objective. These include completing the first tape-out that we internally funded in nearly a decade. The SRH FPGA technology we've developed is the foundation of our storefront model and getting a 12LP test chip in the hands of the DIBs that are developing strategic defense systems today is a critical element to our success. The importance of demonstrating our SRH FPGA test chip goes well beyond the storefront designs we believe it will enable us to secure. FPGA is the number one spending category for semiconductor devices by the defense industrial base, and custom ASICs are a close second. Together, we believe these two categories make up roughly half of the DIB semiconductor TAM. We expect many of these new strategic designs will use either discrete FPGA devices that we can storefront or embedded FPGA IP we can license in new ASIC designs. By delivering a discrete SRH FPGA test chip fabricated on the 12LP process, we are demonstrating the broader capability of our eFPGA hard IP for ASIC applications that will need to either be radiation-tolerant or rad-hard. We introduced Australis in 2021. It is a proprietary tool that we use internally to quickly generate customer-specific eFPGA hard IP, and it provides us with a substantial competitive advantage. While we have refined Australis through the years to enhance these advantages, the release of version 2.0 will mark its first significant update. Our success in advanced fabrication nodes, which include 12-nanometer nodes at GlobalFoundries and TSMC and Intel 18A have led to customer contracts and engagements for very high-density eFPGA IP cores that will require the advancements we are introducing with Australis 2.0. These include an awarded 12-nanometer contract, a pending 12-nanometer contract and a potential Intel 18A contract for a 1 million-plus lot production design. We are also seeing customer requirements for faster core speeds, improved silicon utilization, and certain new features for high-reliability applications. Australis 2.0 will support these requirements and more. Due to these factors, we have given Australis 2.0 a very high priority. We are confident that we will deliver our first eFPGA hard IP using Australis 2.0 for an existing revenue-generating contract during Q4. While we are also confident this will contribute to a substantial sequential increase in Q4 revenue, some of the revenue that we've pushed forward may extend into early Q1. Due to this, we are conservatively projecting a modest decrease in full-year 2025 revenue relative to 2024. Australis, including the soon-to-be completed version 2.0, is our proprietary hard IP generation tool that we use internally. Aurora is the development tool we provide to our customers. The two tools work hand-in-hand and together optimize the efficiency of the design process, hard IP generation, and the resulting PPA of the silicon implementation. PPA is an industry term meaning power, performance, and area. Aurora started out as a development platform with open-source synthesis, which was fine for trailing-edge fabrication nodes and low-to-medium-density designs. However, many of the large customers we are currently engaged with prefer the Synopsys Synplify FPGA design tool, which is particularly beneficial for leading-edge fabrication nodes and high-density designs. To accommodate this requirement as quickly as possible, we adopted Aurora 2.9 to be compatible with Synplify and branded it Aurora Pro 2.9. We discussed this in our February conference call. Since then, we've worked closely with Synopsys to optimize Synplify for our proprietary architecture and seamlessly integrated it into Aurora Pro. This was covered in a press release issued July 28. The integration of Synplify is tailored to QuickLogic's eFPGA architecture and includes optimizations for embedded carry chains, block RAM, and DSP blocks. This significantly reduces critical path delays and accelerates design convergence, resulting in up to a 35% improvement in maximum frequency. This integration also delivers up to a 50% improvement in resource utilization as demonstrated by customer designs achieving over 96% lot utilization. Now a brief update on our U.S. government SRH FPGA contract. Q3 will mark the low point for revenue recognition this year on our U.S. government SRH FPGA contract. We completed our deliverables on schedule and recognized the associated revenue during Q2. We are now waiting on the completion of key deliverables from a subcontractor. Due to this, revenue recognition from our SRH FPGA contract will be de minimis in Q3, followed by an anticipated rebound in Q4 that is funded by the current tranche. As we previously announced, we delivered customer-specific eFPGA hard IP for a customer test chip targeting Intel 18A late last April. This test chip is moving through fabrication, and we expect to have our allocation of test chips to be in hand for evaluation towards the end of Q4. We have booked a second test chip contract with this U.S.-based customer valued at $500,000 that is scheduled for delivery in Q3. In addition to this, we have also been awarded a six-figure feasibility contract for a 1 million-plus lead design that we are scheduled to complete in Q4. We anticipate this will lead to an eFPGA IP contract for a high-density chiplet design during the first half of 2026. In our May conference call, I stated that a mid-7-figure contract with this customer targeting Intel 18A was delayed due to the timing of government funding. The customer advised us that it was awarded funding for the program, but funding for the production ASIC, which is a subcomponent of the program, would not be awarded until Q4. Beyond the base of business we are rapidly building with this customer, we have multiple Intel 18A engagements with other DIBs and with commercial customers that we believe will result in significant contracts beginning in Q4. Last quarter, I mentioned that we were in early discussions with customers regarding a digital proof-of-concept chiplet strategy that would give them a head start in chiplet development while standards are still in a state of flux. These discussions have expanded to include two of our large strategic partners who will actively help us promote the digital proof-of-concept chiplet we have jointly specified directly to potential end customers as a QuickLogic storefront device. Due to the fact we can leverage our existing library for the eFPGA core in the chiplet and integrate that with readily available third-party IP, the digital proof-of-concept chiplet will be completed before our next conference call and will be a low-cost investment with potentially very high return as a storefront device. It will be designed to target any of the advanced fabrication nodes we've discussed and can be easily modified to fit customer-specific requirements. Please note this digital proof-of-concept chiplet initiative will not utilize any engineering resources that we have dedicated to Australis 2.0, our 12LP SRH test chip or revenue-generating hard IP contracts. Before turning the call over to Elias, I would like to take a moment to acknowledge the passing of Christine Russell, who served as a QuickLogic Board Director and Audit Committee Chair for two decades. She was a dear friend and will be missed. Ron Shelton has joined as a new member of our Board of Directors and will assume the role of Audit Committee Chair. Ron has served as Chief Financial Officer for both public and private semiconductor companies for more than 25 years and is very well respected across Silicon Valley. Ron is also very well connected with investment bankers and analysts, some of whom already cover QuickLogic. We look forward to his strategic insights and guidance contributing to the company's continued growth and success. With this, I will turn the call over to Elias for financial results and outlook.

Thank you, Brian, and good afternoon, everyone. Total second quarter revenue was $3.7 million. Total revenue was down 10.7% from Q2 2024 and down 15% compared to Q1 2025. Revenue was below the midpoint of guidance due to lower discrete FPGA revenue and slightly lower revenue recognition from existing IP customers than we had forecasted. New product revenue in Q2 was $2.9 million, down 4.5% from Q2 2024 and down 22.3% compared to Q1 2025. Mature product revenue was $0.8 million, down from $1.1 million in the second quarter of 2024 and up from $0.6 million in the first quarter of 2025. Non-GAAP gross margin in Q2 was 31%. This compared with non-GAAP gross margin of 54.4% in Q2 2024 and 47.1% in Q1 2025. The primary reason this was below our outlook include the fact approximately $350,000 of R&D costs that we projected would be allocated to OpEx were instead allocated to COGS. In addition, we took an inventory reserve of a little over $100,000. Beyond that, it is attributable to less favorable absorption of fixed costs due to lower-than-anticipated revenue, product mix, and certain investments that have been detailed by Brian. Non-GAAP operating expenses in Q2 were approximately $2.5 million. This was approximately $350,000 below the low end of our outlook due to the COGS allocation I just mentioned. This compares with non-GAAP operating expenses of $2.9 million in the second quarter of 2024 and $3.1 million in the first quarter of 2025. Non-GAAP net loss was $1.5 million or $0.09 per share. This compares to a non-GAAP net loss of $0.7 million or $0.05 per share in Q2 2024 and a non-GAAP net loss of $1.1 million or $0.07 per share in the first quarter of fiscal 2025. The difference between our GAAP and non-GAAP results is related to noncash stock-based compensation expenses, impairment charges, and restructuring costs. Stock-based compensation for Q2 was $0.8 million. Impairment charges for Q2 were $0.3 million and restructuring costs for Q2 were $21,000. Stock-based compensation was $0.9 million in Q2 2024 and $0.9 million in Q1 2025. Restructuring costs were $0.1 million in Q1 2025. For the second quarter, three customers and one distributor accounted for 10% or more of total revenue. At the close of Q2, total cash was $19.2 million, inclusive of utilization of $15 million from our $20 million credit facility. This compares with $17.5 million, inclusive of usage of $15 million from our $20 million credit facility at the close of Q1 2025. Net of the approximately $2.9 million raised in ATM sales during the quarter to support the strategic objectives Brian has outlined, our cash usage in Q2 was approximately $1.3 million. Now moving to our guidance and outlook for our fiscal third quarter, which will end on September 28, 2025. Revenue guidance for Q3 2025 is approximately $2 million, plus or minus 10%. Third quarter revenue is expected to be comprised of approximately $1.1 million in new products and $0.9 million in mature products. As Brian stated in his remarks, our decision to focus engineering resources on the tape-out of our SRH FPGA test chip and the accelerated introduction of Australis 2.0 pushed out deliverables and the associated revenue recognition for several contracts. This decreased our revenue outlook for Q3, but it is expected to fuel a substantial increase in Q4 revenue. Based on the anticipated Q3 revenue mix, non-GAAP gross margin for the third quarter is expected to be approximately 5%. The lower gross margin is attributable to the unfavorable absorption of fixed costs due to lower anticipated revenue. With the significant revenue rebound we anticipate beginning in Q4, we are modeling full-year 2025 revenue will be modestly lower than 2024 and full-year 2025 non-GAAP gross profit margin in the low-to-mid 50% range. Our Q3 non-GAAP operating expenses are expected to be approximately $3.2 million, plus or minus 5%. We are modeling our non-GAAP OpEx to be approximately $12 million for fiscal year 2025. Please note that given the nature of our industry, we may occasionally need to classify certain expenses to COGS versus OpEx or capitalize certain costs. The classifications are related to labor and tooling for our IP contracts with customers. This may cause variability in our quarterly gross margins and operating results that we usually balance out on the operating line. After interest and other income, we forecast that our Q3 non-GAAP net loss will be approximately $3.2 million to $3.4 million or $0.20 to $0.22 per share. The main driver between our GAAP and non-GAAP results is related to noncash stock-based compensation expenses. In Q3, we expect this compensation will be approximately $0.9 million. This is the same as Q2 2025 and is down $300,000 from Q3 2024. As a reminder, there will be movement in our stock-based compensation during the year, and it may vary each quarter based on the timing of grants. We're anticipating Q3 usage will be similar to Q2 '25 and rebound to solidly positive cash flow and non-GAAP profitability in Q4. Thank you all. With that, let me now turn the call over to Brian for his closing remarks.

Thank you, Elias. The decisions we made during the second half of Q2 to prioritize the tape-out of our SRH FPGA test chip on GlobalFoundries 12LP process and maintain the accelerated release schedule for Australis 2.0 were not made lightly. While these decisions have dramatically reduced our revenue outlook for one quarter, the upside potential of the investments is exponential. With these investments, we have an opportunity to accelerate our storefront business model and significantly expand our served available market to address applications that require high-density FPGAs. This is a very large market that is currently dominated by discrete FPGAs from our largest competitors. Expanding our capability to integrate these traditionally discrete FPGA designs into ASICs using Australis 2.0 is a huge opportunity for QuickLogic that we will be ready to execute in Q4. I realize we have provided a considerable amount of new information today. Due to this, we've done our best to keep our presentation concise today to allow more time for your questions. With that, we will now open the call for Q&A. Alicia, back to you.

Our first question comes from Rick Neaton with Rivershore Investment Research.

In asking digging into your strategic decision to advance the test chip in Australis over more certain business that could possibly have accrued in Q3. It sounds like from your descriptions of the density of some of what you're targeting that you're actually targeting the most widely known competitors in the FPGA market, namely Intel's Altera, while it's still at Intel and AMD Xilinx in the U.S. How quickly can this particular defense business ramp in the storefront business over the coming quarters? Can you give us some color on that?

Yes, I can. And I think one of the points we're trying to convey in the prepared remarks is just how fast this is moving with the engagement with the defense industrial base and what accelerated, in particular, the tape-out that we funded on the strategic rad-hard FPGA. So I think the short answer is that we could start seeing some test chip revenue very early 2026, and we're anticipating having some of these devices on boards for customer engagement. And that's based on our ability to supply those. If we think about the demand side, conversations I've been having over the last couple of weeks have really emboldened us to go and accelerate this tape-out because I think we can all see from the news that there is a tremendous push not only to strengthen the systems that give us national security, but to do those in a way that they're manufactured and fabricated in onshore foundries. And if we look back at the last two years of the developments that we've been doing, more often than not, our eFPGA IP core developments have been in U.S. foundries. With GlobalFoundries on 12LP and 22FDX and with Intel on 18A. And I think knowing that, that demand is there, I think we've said multiple times now the DoD spends north of looks like $5 billion a year on semiconductors. And I think roughly half of that is a mix of FPGA and ASIC. So the sooner we can get an FPGA test chip taped out and manufactured in the hands of people, we can start engaging on storefront revenue on that. The sooner we can get IPs done, we can start getting inserted into ASICs, that's the number two category. And of course, we can start monetizing that when we license. But again, back to your direct storefront question, I think the fact that we're taping this out now gives us the ability to start monetizing from test chips perspective in 2026. And who knows, that could lead to even end of year or early 2027 for more volume-oriented device sales on that technology. So I think it's absolutely the right decision that we accelerated that because if you're thinking about, do I do $1 million or $2 million more revenue this quarter and then forgo the chance to get into multi-hundred million dollar markets in the defense area with all this going on and these new systems being deployed, that's the wrong decision for investors. The right decision is to make sure that we have the chips on the table for when these companies are making these decisions on microelectronic components that go into the national defense types of systems that are going to be coming online in the next few years. And that's the bet that we've made. And I think that's absolutely the right bet to do that.

How closely are you engaged with these prospective customers that you feel certain enough to make this change in course and actually do a tape-out because over the last few years, you've talked about the benefits of just licensing IP, getting royalties and then perhaps some limited storefront activity. So how engaged are you with these people that you made this change of course?

So I'd say, firstly, that we've been on the path of doing developments for storefront for the last several years. IP has obviously been a big part of the business model as well. But we had our eye that we wanted to have more products or capability on the storefront side because we know that those drive the top line considerably higher and faster than IP licenses. So having this blended business model was the right model for the company. As you know, since our inception 35 years ago, whatever it is now, defense has always been a big market for QuickLogic. And I've always been very connected to that industry as well, dating back to when I first started here. I'd say in the last few years, the activity has really picked up in that area as far as customer engagement goes. Some of it just typical discussions you have with existing customers. Some of it's been accelerated because of the exposure that QuickLogic is getting from doing work for the government directly now and also some of the speaking engagements we've been afforded at these big foundry events like the one with Intel Direct Connect a few months ago. And I think those discussions have led to much deeper discussions around program needs and architecture needs. And again, just in the recent time, you can see that there is a concerted push by our government to have onshore manufactured alternatives to what has historically been an overseas manufactured technology, semiconductors and more specifically FPGAs. I can tell you that when it comes to deciding to self-fund a tape-out, and we haven't self-funded a tape-out in nearly a decade, no exaggeration. I take that very seriously. And I am talking directly to these customers to know that there is actually an opportunity to serve there that we solve a problem, a fundamental problem that they have budget to do, and they want to use these parts. And so that's what gave me the confidence and the team the confidence to do that. And I think that also gave the team a lot of motivation, the engineering team in particular, to work nights and weekends to get that tape-out done so that we could intercept the MPW schedule. And kudos to them for doing that because I think they also believe and see the opportunity that's steering right in front of us. Does that answer your question?

So you talked about intercepting the schedule. Are you trying to displace an existing vendor? Or is this something different?

I would say this is something different because if you think about certain programs, certain programs are not able to use offshore manufactured capability. It has to be onshore. And today, there's no production FPGA that's manufactured onshore, not the least of which would be, is it rad-hard? Is it some of these other capabilities that we're talking about. So we're doing this because we want to be a viable alternative to what people historically do, which is go spend a lot of money doing a custom ASIC. When we have standard products available, that's great because they're available immediately. They don't have to wait for an ASIC design cycle. They don't have to spend a ton of money on NRE to go do an ASIC design from scratch. And if you think about, again, the rate at which things are changing and the government is trying to get the defense industrial base to launch these new systems, their schedules and budgets don't really afford for the huge expense of ASICs every time. And so in that case, we would actually be an architecture alternative to what has classically just been full custom ASIC path.

Our next question comes from Richard Shannon with Craig-Hallum.

Brian, you've certainly made this call very interesting. I had prepared extensively, but much of that has changed considering the intriguing developments we've discussed. I have a couple of quick questions, starting with a follow-up on Rick's question. This relates to whether there are any alternatives. You mentioned earlier that there haven't been any in the past. So, to your knowledge, do you know if anyone else is attempting something similar? Is it possible for someone to replicate this only with embedded FPGA technology, or could it be achieved in another way?

I think at the end of the day, if you want custom capability implemented in a microcontroller or a microelectronic device, you can do that as an ASIC or you can do it in an FPGA. And so do I know if anybody is doing an FPGA that's doing what we're doing? I don't think so. There are clearly other FPGAs in the market that are rad-tolerant, less that are rad-hard, none that I know of that are strategic rad-hard and none that I know of that are on GlobalFoundries 12LP. So I think we're pretty well positioned for the capabilities that we have designed into our chip to be very unique and different. And that's what's driving a lot of the interest in the defense industrial base to get their hands on these as soon as we can get them to them.

Okay. So the tenor of these conversations leads you to believe strongly that these are dependent on executing our sole source positions.

I would not have authorized this PO if I didn't think there was a very high degree of confidence in winning actual revenue, and I'm talking about the hundreds of millions of dollars of revenue if I didn't truly believe that this was a differentiated and very good investment for us and our stockholders.

Okay. That's very directly stated. Maybe a few other key details on this initiative here. So are all of these opportunities you're going after specifically related to Golden Dome or are they a little bit more broadly across new defense programs? Just want to be clear since that was part of your remarks.

It's much broader than that. We inserted Golden Dome in this just because there's been a lot of press about that recently. And I think there's been a lot of meet-ups, if you will, within the industry around Golden Dome and how that can be accelerated. But this is clearly not limited to Golden Dome.

Okay. And are these all rad-tolerant or rad-hard?

Yes. The second you start backing off of rad-hard, rad-tolerant and you're talking about just plain COTS mil-temp, that really opens up a much broader competitive arena. And we're really trying to stay focused in the swim lane where we can be very dominant and very differentiated. And so we are trying to stay focused on rad-tolerant and rad-hard. If an engagement leads in a different direction to mil-temp plastic parts, fine, we'll talk to anybody that wants to buy our devices, but that's not the main thrust behind this.

Okay. And then I'm pretty sure I understand this, but I'm asking a very direct question here just to make sure that I do. So all these devices are inherently higher density that you wouldn't expect to be done on other nodes, specifically the rad-hard you're doing with two other foundries you've been working on for a couple of years here. These are not overlapping markets in any way, are they? So this is entirely new. Is that correct?

This is entirely new. This is funded by QuickLogic, completely independent.

Okay. But not overlapping in market in any way.

Not that I am aware of. I mean there's a definition for what a supersede and a subset are, which is somewhat ambiguous, right?

But I guess my point is it sounds like you're describing this as really high-density stuff on a 12-nanometer node that you wouldn't inherently be able to do on a 90-nanometer node you've been working on with others.

Yes, for sure. Yes, I completely agree.

Okay, perfect. I have two last questions. I'll step out of line here. It seems that you're postponing some of the contracts we've heard about for several quarters in past calls. Are there any negative consequences for these contracts due to the delays as you concentrate on this?

No. In fact, the schedules that we're talking about with customers as a result of the Australis 2.0 capability being prioritized, we're being very forthright with our customers. There's no issue with that. They're working with us on those deliveries. And there's no material impact at all to things that we have in our contract. It's helping shape how we discuss and negotiate contracts for the ones that aren't won yet, but they're very clear in understanding of what Australis 2.0 has. And like I was saying in the script, some of these customers that we've been engaged with, their desires from our core have actually expanded, and that's what's driven us to actually accelerate Australis 2.0 so that not only can we do the core they need, but we can do it and still have this automation that we need so that we can actually handle multiple cores for multiple customers at the same time. We could have gone and prioritized, well, let's just do this one customer for revenue in Q3 and let's push out 2.0. And that's the whole thing I was mentioning earlier that we could do that, and that's better for Q3 revenue, but it's actually not better for the company because then we're still in the same situation waiting for 2.0. So this is the bite the bullet, get 2.0 out and done so that we can then use that to fan out to these multiple customers that we're talking about, especially the ones that need the higher density. And we are starting to see more of those now. And that density range clearly needs Australis 2.0. So the sooner we can get that done, the sooner we can start tackling many of these in parallel.

Okay, that makes sense. I appreciate all the details. I have one last question for Elias. I would like to narrow down a bit on your thoughts regarding the modest decline in revenues and what that might mean for fourth quarter revenues. If you could define or help us understand those numbers, it would be greatly appreciated.

We anticipate a noticeable increase beginning in Q4, but we still expect a slight decline compared to last year. I am not ready to provide a specific number at this moment, but we are actively working on it. I would prefer to wait before sharing any figures because I don’t want to overcommit. However, I can say that the increase we expect is significant.

Okay. Fair enough. I guess we'll try our best on modeling that, and we look forward to very interesting next few quarters.

Our next question comes from the line of Gus Richard with Northland Capital Markets.

I just had a couple of questions. The first one is, I never heard of a chip company monetizing a test chip. And I believe in the script, you said that you'd be able to get customers to pay for test chips, and it sounded like you were going to sell multiple test chips. I'm just wondering how that works.

Yes, absolutely. Test chips are our method of validating IP functionality before we move to the production version, as this helps reduce risk and initial costs. However, you can certainly sell devices to customers as engineering samples. In this context, test chips and engineering samples can be considered synonymous. When providing customers access to technology, particularly in the markets we are discussing, it is common for them to be willing to pay for such technologies, especially when they are offered in a user-friendly format like an evaluation card. Customers in these sectors are generally accustomed to compensating for this, unlike a decade ago when companies in the consumer market expected free prototypes until a significant purchase was made. The aerospace and defense sectors present a different scenario. Therefore, we anticipate that they will be paying for these test chips.

So the test, if I've got this right, and you say it's interchangeable with an engineering sample. So this is a fully functional stand-alone FPGA test chip. Is that the way to think about it?

That is the way to think about it. That's right. We've designed it so that our customers can take their IP, their RTL and run it in the FPGA in that test chip.

I see. So it would go along with the demo board or what have you?

Yes, they would get some sort of an evaluation board and then the FPGA user tools, the Aurora tools that we provide for them to run their designs through and create a bitstream.

Got it. And could this test chip be turned into a standard product? Or would there be more engineering required before that would happen?

That's a crucial question because if our customer evaluations are successful in that they can operate their RTL with minimal changes, we can proceed directly to production. If, during the evaluation process, we find that we need to make adjustments—such as increasing or decreasing size or adding a different interface—these modifications are typically manageable but could affect our timeline and development costs. This is why we aim to provide the test chip to the defense industrial base; there's no substitute for them using and assessing the component with their software to determine if it functions as intended or requires modifications. Engaging with them through this process is vital, which is why we made the careful decision to expedite the testing phase to gather their feedback. We need to understand if this product can work effectively and potentially start generating revenue by the end of the year, depending on the nature of any necessary adjustments.

Will this go through on a hot lot? Is it a multi-project wafer? What is the mechanism globally?

I'm going to provide a bit more detail. However, if we delve deeper, I may refrain from going further. Typically, companies utilize multi-project wafers because it helps reduce the cost of the test chip. That was one of the reasons we hurried to complete and submit our work on time, as there was a multi-project wafer we aimed to connect with. Multi-project wafers are like the Shinkansen in Japan; if you are even a minute late, you miss your opportunity. Our engineering team did a fantastic job ensuring everything was submitted promptly so we could catch that multi-project wafer opportunity. In short, that's the rationale behind utilizing multi-project wafers, and I hope that answers your question.

Yes. If this chip is successful, you would need to process more full wafers to provide samples to customers.

And that's a great problem to have. Global is a fantastic foundry, and I have no doubts that they could handle that if we need it.

Okay. And at the risk of boring everybody, shifting over to the software side, it sounds like you have been using your engineers that work on the design software to help customers design products in your FPGAs, and you're taking those customers out of customer support and moving into product development. Is that the way to think about it?

We have different disciplines within engineering. Some people tend to be more customer-focused and some are more internally focused. There are some resources that can cross over those domains and do both. And I would say that anybody that could help with getting this tape-out done helped without impacting customer-related programs. So we did do a lot of resource shuffling to make that happen.

Yes. I was referring to the software side, your design software. It sounded like a customer's project was delayed for revenue in Q3 because you're working on your design software.

That's Australis. So Australis is the IP generator. Australis 2.0 needed to go through several feature enhancements to meet the needs of what I was just talking about earlier. And we were basically trying to pull that in and accelerate that. And we're still working on that because we said 2.0 will be available in Q4. And so there are as many resources that we have that are capable of helping with Australis 2.0. We're doing that because we want to get that done and ready in Q4. We don't give Australis to our customers. Our IP engineers use Australis to create IP for customers.

Our next question comes from the line of Richard Shannon with Craig-Hallum.

Brian, just one follow-on question for me. So you talked about this great deal of interest from various defense programs and specifically the need for onshore manufacturing. You're obviously talking about rad-hard, rad-tolerance on a 12-nanometer node. Does this enthusiasm and acceleration of timeframes, are you also seeing this in your strategic rad-hard on the other two foundries you've talked about working with for the last couple of years?

We are definitely seeing interest on the DIB on those. I'm not going to be able to go into more detail because that's the government contract, and I'm not allowed. I've asked again for permission to talk about it in more detail, but not been granted that. So I can't really go into more detail. But we are still seeing interest for that as well from an end customer perspective.

There are no further questions at this time. I'd like to pass the call back over to Brian for any closing remarks.

Thank you. Before we conclude, I wanted to share a few upcoming opportunities to connect. On the investor side, we'll be at the Sixth Annual Needham Virtual Semiconductor & SemiCap 1x1 Conference on August 21 and in New York on September 4 for the TD Securities Technology Growth Cap Summit. We'll also be showcasing QuickLogic at key industry events, starting with GlobalFoundries Technology Summit in Santa Clara at the end of August, then in Munich in October; and finally, embedded world North America in Anaheim this November. Thank you once again to our shareholders, analysts and the broader investment community for your continued interest and support. We value your confidence in QuickLogic and look forward to updating you on our progress in the quarters ahead. Thank you, and goodbye.

This concludes today's teleconference. You may disconnect your lines at this time. Thank you for your participation.