Hello, everyone, and welcome to Atomera's First Quarter 2026 Update Call. I'd like to remind everyone that this call and webinar are being recorded, and a replay will be available on Atomera's IR website for 1 year. I'm Mike Bishop with the company's Investor Relations. As in prior quarters, we are using Zoom, and we will follow a similar format. Operator provided instructions. We will open with prepared remarks from Scott Bibaud, Atomera's President and CEO; and Frank Laurencio, Atomera's CFO. Then we will open the call to questions. If you are joining by telephone, you may follow a slide presentation to accompany our remarks on the Events and Presentations section of our Investor Relations page on our website. Before we begin, I would like to remind everyone that during today's call, we will make forward-looking statements. These forward-looking statements, whether in prepared remarks or during the Q&A session, are subject to inherent risks and uncertainties. These risks and uncertainties are detailed in the Risk Factors section of our filings with the Securities and Exchange Commission, specifically in the company's annual report on Form 10-K filed with the SEC on February 24, 2026. Except as otherwise required by federal securities laws, Atomera disclaims any obligation to update or make revisions to such forward-looking statements contained herein or elsewhere to reflect changes in expectations with regards to those events, conditions and circumstances. Also, please note that during this call, we will be discussing non-GAAP financial measures as defined by SEC Regulation G. Reconciliations of these non-GAAP financial measures to the most directly comparable GAAP measures are included in today's press release, which is posted on our website. Now with that, I'd like to turn the call over to our President and CEO, Scott Bibaud. Go ahead, Scott.

Thanks, Mike, and good afternoon, everyone. This quarter, we made solid progress with multiple customers across our highest-value markets while also expanding the breadth of applications where MST can solve real current pain points for the semiconductor industry. We're seeing strong customer pull in advanced logic, memory and wide band gap materials like GaN and power and in RF, areas that are being shaped by the rapid growth of AI infrastructure, which is driving the need for better power efficiency, signal integrity and system performance. Today, I'll start with an update on gate-all-around, where we've been working closely with customers and our strategic partners to validate MST in these advanced geometries. Then I'll touch on our customer pipeline and close with updates on GaN, giving insights on some exciting new technical results that are shaping near-term opportunities. As we said before, the move to gate-all-around at 2 nanometers and beyond is one of the most important architectural transitions in the industry, and it's also one of the most difficult manufacturing environments since fabs must build incredibly complicated structures at line widths of 5,000x smaller than a human hair, where a small amount of atomic migration can cause big problems. Gate-all-around transistors are the building blocks for AI infrastructure and dopant diffusion control is critical to their effectiveness in terms of performance and reliability. Therefore, the industry is demanding clear proof that any new material can be deposited precisely and that it delivers measurable benefits in advanced silicon devices. Today, there are 4 companies in the world developing gate-all-around transistors, TSMC, Samsung, Intel and Rapidus. We know that each of them can use the capabilities of MST, so it's our goal to achieve adoption at all 4. Further, as these companies transition to the generation beyond gate-all-around called CFET, our technology becomes even more essential. So working with us now is in their best interest long term. In our last earnings call, we just received measured silicon results that prove MST is the best solution for a critical source strain liner application in these small geometry transistors. At this point, we're actively working on evaluations of our technology with 2 of our target gate-all-around customers and discussions are underway with the others. It is typical that a customer asks to conduct multiple demonstrations before agreeing to accept a new technology for implementation in their fab wafer flow. These demonstrations help to validate our claims while simultaneously addressing the detailed implementation and functionality questions these customers are focused on solving. We also expanded the scope of our work with our strategic development partner this quarter, which is important because it strengthens both our technical velocity and our credibility with the ecosystem. Their test and development infrastructure helps us generate the kind of data that advanced node customers insist on seeing before engaging and their endorsement will certainly help us engage a broader set of teams within each target account. Each of the large memory manufacturers are facing similar challenges to the gate-all-around customers as they develop their next-generation transistors in DRAMs and high-bandwidth memories. Our team is in discussions with them right now, and we are currently working on multiple solutions using MST to assist in this area. Right now, memory manufacturers would do almost anything to get greater fab capacity, and they have the resources to evaluate different methods of doing so. We hope to take advantage of that opportunity with solutions enabled by MST. The momentum we're seeing in the advanced node transistor space is a result of many years of work targeting current market trends. The macro challenges that AI success has put front and center, capacity and performance of CPUs, GPUs, logic and memory, the power demands of cloud providers and the increased costs associated with these are all areas that Atomera can help solve. For that reason, we believe that MST is a fundamental tool for the future of AI. Our customer pipeline remains very active across multiple domains. For example, our work with our large IDM customer continues to go well, and we expect additional results from wafer runs soon. Our efforts with ST Microelectronics are bearing fruit, and we are confident we will reengage with them again in the near future, consistent with our view that MST can create value across multiple product lines, especially in a large diversified IDM or foundry. In RF SOI, we are seeing strong results confirming our extensive TCAD simulations. The technical results we've been focused on, including for both power switch and LNA have been confirmed through customer silicon runs. The near-term question is less about performance and more about the most efficient path to commercialization, particularly in cases involving fabless licensees where aligning the business structure with the manufacturing flow can be complex. In power devices, we're seeing excellent potential in new development work being done to target MST at both TrenchFET and HVT transistors, useful in high-frequency, high-speed and high-voltage applications. At the same time, wafers continue moving forward with our second JDA partner, and we'll keep pushing those efforts toward production pathway. Turning to GaN. We made meaningful advancements this quarter, including a breakthrough that could give us a technical leadership in RF GaN on silicon to augment the advantages previously outlined for power GaN on silicon. To explain the innovation, I need to give a little background. GaN on silicon is a much more economical growth method than alternatives built on exotic substrates like silicon carbide or sapphire. But when GaN on silicon is manufactured due to the GaN stack growth process, gallium and aluminum ions gather at the silicon substrate interface, forming an unwanted sheet charge layer called a parasitic channel, which is well known to limit RF performance and GaN on silicon applications. In fact, its elimination has been the subject of materials and growth studies for more than 20 years. In the past few weeks, we received preliminary performance data suggesting MST can dramatically reduce the parasitic channel. It does this by using MST's fundamental interface engineering to block the gallium and aluminum ions from getting into the silicon substrate. An industry veteran told us that in his 20 years, this is the best measured sheet charge data he has ever seen. We're continuing to validate this very promising discovery with our test and measurement partners. RF GaN on silicon is a value in the wireless infrastructure, military, defense and satellite markets. It's also being actively evaluated for high integrated RF front ends such as those for 6G cellular. So the market potential is large and growing fast. We are actively engaging on both 200-millimeter and 300-millimeter wafer sizes in GaN depending on our customers' requests. That matters because the wafer size for GaN on silicon is one of its key advantages leading directly to a customer's path to high-volume production, low-cost structure and a set of fabs that can support ramp, including opening doors for new applications with conventional silicon fabrication methods and devices. We're seeing expanded interest in partnerships across the ecosystem, including engagements involving Incize, Synopsys, Texas State University, Sandia and others. Those kinds of parallel tasks, commercial customers plus research and ecosystem partners can compress development cycles and accelerate the time from promising materials data to something customers can qualify and deploy. Work here is aimed at generating data that is both technically rigorous and directly translatable to customer device requirements. Finally, a quick note on our announcement last week about expanding our collaboration with Synopsys. We've worked with Synopsys for years to enable accurate modeling of MST inside the Sentaurus TCAD environment through our MST CAD tool set. This expanded collaboration extends that relationship into GaN workflows for both high-value RF and power devices. Practically, this means we're working closely with Synopsys to provide feedback on their GaN models, and we'll be jointly developing marketing materials so customers and partners can evaluate the physical and electrical effects of MST and GaN more quickly and with higher confidence. To summarize, we're making progress where it matters, expanding and deepening gate-all-around engagements, broadening GaN from power into RF with concrete technical innovations and continuing to advance multiple customer programs across our pipeline. We remain focused on converting technical validation into commercial structures that can drive repeatable revenue and are confident in our ability to do so. This is indeed an exciting time for Atomera. With that, I'll turn the call over to Frank, our CFO, to review our financials.

Thank you, Scott. At the close of the market today, we issued a press release announcing our results for the first quarter of 2026, and this slide shows our summary financials. Our GAAP net loss for the first quarter of 2026 was $6.1 million or $0.17 per share compared to a net loss of $5.2 million, which was also $0.17 a share in Q1 of 2025. On a non-GAAP basis, net loss last quarter was $4.9 million or $0.14 a share. And our Q1 2025 net loss was $4.4 million or $0.15 a share. GAAP operating expenses were $6.2 million in Q1 of 2026, which was an increase of $742,000 from $5.5 million of GAAP operating expense in Q1 2025. Stock compensation expense, which is excluded from non-GAAP results, increased by $397,000, primarily due to new hires and our adoption in Q1 of 2025 of performance stock units, or PSUs, for executives. PSUs vest over 3 years, whereas the time-based options and RSUs that we had previously granted to executives vested over 4 years. Although the vesting period is shorter, PSUs vest only if our stock performs well relative to the Russell 2000. The first tranche of PSUs issued in Q1 2025 lapsed without vesting because we did not hit the required stock price performance threshold. With the exception of stock compensation expense, the drivers of GAAP and non-GAAP expenses are substantially the same. So I will drill down into other factors that impacted our expenses by focusing on non-GAAP numbers. Please refer to the slide presentation for a reconciliation between GAAP and non-GAAP results. Non-GAAP operating expenses in the first quarter were $4.8 million, a year-over-year increase of $348,000 from $4.4 million in Q1 2025. Sales and marketing expense increased by $203,000, reflecting our 2 executive hires since October. R&D expenses increased by $127,000 from $2.8 million in Q1 of last year to $2.9 million in the first quarter of this year, primarily due to higher spending on outsourced engineering to support the wafer runs for our gate-all-around engagements, our IDM customer and our JDA customer, which drives spending on metrology. G&A expenses were basically flat from the first quarter of last year. Turning to sequential quarterly results. First quarter 2026 non-GAAP net loss was $4.9 million or $0.14 a share compared to net loss of $3.3 million or $0.10 a share in Q4 of 2025. Operating expenses were $4.8 million in Q1, which is a $1.6 million increase from $3.2 million in Q4. Let me offer some color on the magnitude of the sequential increase. As I explained on our last quarterly call, our Compensation Committee elected not to pay the full 2025 executive bonus, withholding approximately $669,000, which normally would have been paid out in January. The committee provided the executive team the opportunity to earn back the withheld amount in 2026 upon achievement of commercial objectives. This led to us reversing accrued bonus expense in the fourth quarter, which skews the comparison of expenses between Q1 and Q4. Our balance of cash, cash equivalents and short-term investments on March 31, 2026, was $41.1 million compared to $19.2 million on December 31, 2025. We used $4.6 million of cash in operating activities during Q1 compared to $3.2 million in Q4 and $4.8 million in Q1 of last year. As is typical for us, cash used in the first quarter of every year is higher than other quarters due to payments for items that are expensed over the year. In February of this year, we closed on a $25 million registered direct stock offering, selling 5 million shares of common stock at $5 per share, netting us proceeds of $23.6 million after fees and expenses. Prior to this offering, we had also raised $3.2 million in Q1 by selling approximately 1.3 million shares under our ATM at an average price of $2.47. Currently, we have 38.7 million shares outstanding. With the proceeds of our equity offering, we feel that our current cash balance puts us in a strong position to execute on the opportunities ahead of us, but we will continue to be disciplined about controlling our costs. On our last call, I said that we expected our 2026 annual non-GAAP operating expense to be approximately $18.5 million, and we are holding to that number. To reiterate, the reason why the expense increase appears as large as it does over $15.9 million of OpEx in 2025 is the bonus deferral, which essentially shifted expenses out of Q4 and moved them into 2026. Organic increases in spending mainly relate to the hiring of our VP of Sales in Q4 last year and our VP of Marketing in Q1. Revenue in Q1 was $11,000 and consisted of fees for wafer deliveries to the large IDM that Scott talked about. And we have $96,000 of deferred revenue on our balance sheet. Approximately $46,000 of revenue that we expected to recognize in Q1 pushed out to Q2 because wafer shipments that we anticipated making last quarter pushed out to early this quarter. Accordingly, we expect Q2 revenue to be in the range of $50,000 to $100,000. With that, I will turn the call back over to Scott for a few summary remarks before we open the call up to questions. Scott?

Thanks, Frank. And before we take questions, I want to thank our employees, our customers and our shareholders for their continued support. We're excited about the progress we're making, and we remain focused on translating our growing body of simulation and customer silicon evidence into commercial agreements that can drive long-term repeatable revenue and a strong sustainable business. Mike, we will now take questions.

Operator provided instructions. And right now, it looks like Richard is ready to ask a first question. Richard, please go ahead.

Scott, the gate-all-around stuff here, you made some very interesting comments. I want to touch on a few of these things. So you mentioned that you've got measured silicon results here and your customers have said that they're better than the other solutions that they have. I just want to make sure that that's what you said, and then I have a couple of follow-ups on that topic.

Yes. Are you talking about GaN or gate-all-around?

Gate-all-around.

On gate-all-around, we do have measured silicon results. And we evaluated our results against another method that people in the industry are using to accomplish the same type of thing we're doing, and our results are a significant improvement. So yes, we have definitely had that, and we're showing that to customers.

So to follow up on this, I assume that the measured results are wafers run at one of these four targeted customers. Is that correct? Or is it independent?

In fact, the measured results are something that we did in conjunction with our strategic partner, where they had gate-all-around structures, and we used those devices to grow MST on those gate-all-around structures in the wafer, and then we were able to conduct this testing. So if you think about how we approach customers, we go out and we show customers our simulation data, which we can do without a strategic partner. But then having silicon-tested data is a massive improvement over that. So that's been able to really open the doors for us to get into the customers. The next step from there is the customer will typically say, okay, we can see you did that on your strategic partner's structure. Now we want you to do it on our structure because our structure is different. Everybody is different. And when I mentioned that we have work underway with two of the target customers doing demonstrations, that's the step we're at where we're trying to implement our technology on their structures and show them that. We believe that the step after that will be that they'll have to install MST in their fabs to do any further testing because these structures are so small and hard to manufacture that it's difficult to do a lot more work by having us run demonstrations in our fab.

Okay. So to that point, do you have a commitment to attempt to do this on your customer structures? Or is it just discussions to get that agreed to?

We're working on it with two of them actually. I don't know what you mean by commitment, but they're sending us wafers and we're putting MST on them. So yes, that's pretty committed.

That sounds pretty good. What's the time frame for this work to get done? I assume the analysis can often take a while and these are complex. What's the turnaround time between getting that done, analyzing and getting to that next step?

It's going to take several months. For the work we have to do, we have to do a lot of development to figure out how to grow things effectively in these tiny devices that they're sending us. Normally, when someone sends us wafers, within three weeks to a month we can turn those around and send them back. In this case, my guess is it might take us longer than that, two to three months. Then when they receive them, they have to put them in their fab and run them for several months. So it could be in the order of six months before we start to see results coming out of this. Structural analysis, which is where they are looking at what we did for deposition in those structures and making sure that what we did was appropriate, can be done pretty quickly because you're taking TEM images like electron microscope images and looking at what we did; those results will come quickly, but the electrical results will be the result of running the wafers through the whole line.

Got it. So you're expecting to run wafers from two different gate-all-around customers over the next few months?

Yes.

Going back to my first question and understanding the results you measured with the runs you did with your equipment partner. Do the customers agree that the comparisons you've done with an industry-standard approach to dopant diffusion are better than what they've been able to get internally? Or is this just what your equipment partner concluded for you?

I think there's no doubt that the customers that we've been able to engage with and get into the details, they have been impressed enough that they want to move forward with further demonstrations. So yes, they definitely saw the benefit of using MST to block dopant diffusion in the areas that we're talking about and how it works better than what they're currently implementing.

Some really interesting stuff going on there. Maybe a couple of other quick questions. On the DRAM side, it sounds like you made some progress. But if I compare that with the progress on the logic side, it sounds like the logic is farther ahead than memory. Is that a fair comparison?

Yes, that's true. We are talking with the memory manufacturers, and one thing to note is memory is quite a different architecture than logic. But memory manufacturers are having the same type of dopant diffusion problems with their newer architectures as the gate-all-around folks, and our technology is directly applicable. So we have a lot of interest from DRAM companies. We're also talking to them about other solutions that may help them in different ways. So it's lots of different vectors of engagement with memory companies, including high-bandwidth memory, not just DRAM. But we're further ahead with the gate-all-around customers than we are with memory.

Maybe a question on the GaN side. Previously you talked more about GaN applications in power, but more recently RF. Which one is leading in terms of getting to the next step and adoption—power or RF?

It's interesting. We initially targeted the power market for our GaN on silicon work because the power market is much larger than the GaN RF market today, and our big value there is to improve crystal quality and allow people to manufacture on larger wafers due to less bow and warp and fewer defects. That has inherent value but validating it requires building wafers, building electrical devices and doing extensive testing, which takes time and tuning. With RF GaN, we got some test data we presented at a compound semiconductor conference last week, and there's huge interest. Looking at the early data, it may be enough for someone to adopt us because it's a big breakthrough in an area where the industry needs solutions. In RF, they sometimes don't have to do full electrical testing before deciding to move forward, so although we're earlier in RF, that one could move faster.

One last question about STMicro—I'm not sure if this is the IDM customer you referenced. How are things progressing with them, especially after the pause on the power work you mentioned late last year? Are other applications with them still moving forward as expected?

To clarify, when I talk about the IDM customer, it's not STMicro. STMicro is another IDM, and we think we have a lot of areas to engage with STMicro, separate from the other IDM. We've been talking with multiple business units at STMicro and doing evaluation work. We recently got results that lead us to believe we will start reengaging with them on developing a product. We aren't at the point where we can talk about that yet, and ST hasn't specifically given us permission to discuss details. But we've said since we had to pause the BCD program at ST that we were working with other groups and that our relationship with the company remained strong. They understand MST technology and believe in it. We hope to be able to announce new work with them in the future.

There are a few questions that have been asked in the Q&A line, and I'll just bring them up one by one. The first question is about gate-all-around: given the evaluation periods that we've seen in other areas of Atomera, are there specific milestones that need to be hit to convert these gate-all-around customers into a JDA? And what's a realistic time frame for such a conversion?

At a high level, customers typically want to see four different levels. First, they want to see TCAD results that show potential to deliver performance and understand the TCAD background. Then they want to see that captured on silicon. We've done those two steps in gate-all-around. The next step is to capture that on silicon on their silicon and on their structure—they'll send us wafers and want us to deposit MST and send them back for evaluation. They won't expect perfect performance immediately because there will be tuning required, but it's a proof of concept on their platform. That's the stage we're at with two customers. Beyond that, the stage after that would be where they install and implement MST in their fabs and tune it appropriately—this would typically involve a license and a JDA. These companies do not move fast on legal agreements, but we're working hard and hope to be able to announce them in the near future.

Frank, a question regarding the equity raise. An investor is curious about the background and reason for the third-party private placement. Given the stock price rise, could timing have been better?

One of the comments I've made is that some funding we got was via the ATM at an average price of $2.47, which is roughly where we were trading about 1.5 to 2 weeks before we did the equity raise. The $5 price that we executed on looked like a very good opportunity given what we had seen over the last couple of years and geopolitical uncertainty in mid-February. You can't know how the equity market will perform, but on balance it seemed like a very good opportunity to execute then. The proceeds strengthen our balance sheet and let us work toward commercial outcomes without worrying about day-to-day movements in the stock price or needing to use the ATM to maintain liquidity. With the benefit of hindsight, it's always easier to second-guess, but I think it was a very good decision to execute when we did.

Question on the tool partner: how has your relationship evolved with your strategic partner? Are they providing more engineering personnel, and how has the relationship changed over time?

We try to be good partners with each of the big epi tool vendors. There are three main tool vendors the industry uses, and we want to be able to support customers regardless of tool choice. The tool vendor with whom we have the strategic partnership we've been working with for more than a decade and had a good relationship. Now that we've entered into a strategic partnership, the level of co-development work is at a whole new level. We have weekly meetings with their engineering team where we develop the test data we need for marketing to customers. As customers ask questions and want more demos, we dig in and do that work together. On engineering cooperation, it's at a new level. On marketing and sales, that's new for us as well; we're developing materials for both companies to go into target customers and discuss MST technology. I've calculated that if we are successful licensing our technology, in many cases the tool vendor may make more money from us winning designs than we will, so there are obvious incentives for them to help make us successful. They recognize that, and we're seeing benefits as we engage with customers.

A follow-up: on the timing of gate-all-around customer engagements, on the last call it sounded like we might see several deals in 2026. Is that still possible, or does that sound unlikely now?

We're only in the fifth month of the year, and I'm hopeful every month that we're going to be inking deals. So there's definitely a very strong chance.

Looking across all areas where you are working, which segments do you think are closest to producing a royalty-bearing license?

I previously spoke about wafer-based products, and I think the development effort for wafer-based products is relatively easier. Areas where we're offering wafer-based solutions include gallium nitride and RF SOI, and we have wafer-based solutions in the memory space as well. So one of those could be the fastest. We've also been working on power and RF SOI with customers for a long time, so those could also be quick to market. It's very hard to call with so many moving pieces.

Scott, I'll turn the call to you for closing comments.

I want to thank you all for joining us to hear the progress being made within Atomera. I hope you're feeling the excitement that we are. Please continue to look for our news, articles and blog posts, which are available along with investor alerts on our website, atomera.com. Should you have additional questions, please contact Mike Bishop. We'll be happy to follow up. Thanks again for your support, and we look forward to our next update call.

Thank you. This concludes the call.